Browsing by Subject "VLSI circuits"
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Item Open Access Adaptive routing framework for network on chip architectures(ACM, 2016-01) Mustafa, Naveed Ul; Öztürk, Özcan; Niar, S.In this paper we suggest and demonstrate the idea of applying multiple routing algorithms during the execution of a real application mapped on a Network-on-Chip (NoC). Traffic pattern of a real application may change during its execution. As performance of an algorithm depends on the traffic pattern, using the same routing algorithm for the entire span of execution may be inefficient. We study the feasibility of this idea for applications such as SPARSE and MPEG-4 decoder, by applying different routing algorithms. By applying more than one routing algorithms, throughput improves up to 17.37% and 6.74% in the case of SPARSE and MPEG-4 decoder applications, respectively, as compared to the application of single routing algorithm. © 2016 ACM.Item Open Access Analog CMOS implementation of cellular neural networks(IEEE, 1993) Baktır, I. A.; Tan, M. A.The analog CMOS circuit realization of cellular neural networks with transconductance elements is presented. This realization can be easily adapted to various types of applications in image processing just by choosing the appropriate transconductance parameters according to the predetermined coefficients. The effectiveness of the designed circuits for connected component detection is shown by HSPICE simulations. For “fixed function” cellular neural network circuits the number of transistors are reduced further by using multi-input transconductance elements.Item Open Access Analysis of Lagrangian lower bounds for a graph partitioning problem(Institute for Operations Research and the Management Sciences (INFORMS), 1999) Adil, G. K.; Ghosh, J. B.Recently, Ahmadi and Tang (1991) demonstrated how various manufacturing problems can be modeled and solved as graph partitioning problems. They use Lagrangian relaxation of two different mixed integer programming formulations to obtain both heuristic solutions and lower bounds on optimal solution values. In this note, we point to certain inconsistencies in the reported results. Among other things, we show analytically that the first bound proposed is trivial (i.e., it can never have a value greater than zero) while the second is also trivial for certain sparse graphs. We also present limited empirical results on the behavior of this second bound as a function of graph density.Item Open Access Application-specific heterogeneous network-on-chip design(Oxford University Press, 2014) Demirbas, D.; Akturk, I.; Ozturk, O.; Güdükbay, UğurAs a result of increasing communication demands, application-specific and scalable Network-on-Chips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor System-on-Chips. A challenge in application-specific NoC design is to find the right balance among different tradeoffs, such as communication latency, power consumption and chip area. We propose a novel approach that generates latency-aware heterogeneous NoC topology. Experimental results show that our approach improves the total communication latency up to 27% with modest power consumption. © 2013 The Author 2013. Published by Oxford University Press on behalf of The British Computer Society.Item Open Access Circuit theoretical method for efficient finite element analysis of acoustical problems(IEEE, 1998) Ekinci, A. Suat; Atalar, AbdullahIn the last decade, there has been an outstanding improvement in the computer aided design tools for VLSI circuits regarding solution times and the circuit complexity. This study proposes formulating the acoustic field analysis problem using FEM, and employing the recent speed-up techniques used in the circuit simulators. In this work, total mass, stiffness and damping matrices are obtained using the FE approach, and piped into a computer program which generates an equivalent SPICE compatible circuit netlist. This approach makes it possible to use the most recent circuit simulation techniques to simulate the acoustical problems. The equivalent electrical circuit is a resistor-inductor-capacitor (RLC) circuit containing controlled sources to handle the couplings. The circuit matrices are 6 times larger but are sparser. We analyze these circuits with a general-purpose circuit simulation program, HSPICE, which provides high accuracy solutions in a short time. We also use an in-house developed circuit simulation program, MAWE, which makes use of asymptotic waveform evaluation (AWE) technique that has been successfully used in circuit simulation for solutions of large sets of equations. The results obtained on several problems, which are solved in time and frequency domains using circuit simulators and the FE analysis program ANSYS, match each other pretty well. Using circuit simulators instead of conventional method improves simulation speed without a significant loss of accuracy.Item Open Access Energy reduction in 3D NoCs through communication optimization(Springer Wien, 2015) Ozturk, O.; Akturk I.; Kadayif I.; Tosun, S.Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. Specifically, on a heterogeneous 3D NoC architecture, we explore how different types of processors can be optimally placed to minimize data access costs. Moreover, we select the optimal set of links with optimal voltage levels. The experimental results indicate significant savings in energy consumption across a wide range of values of our major simulation parameters.Item Open Access Fault-tolerant irregular topology design method for network-on-chips(IEEE, 2014) Tosun, S.; Ajabshir V.B.; Mercanoglu O.; Öztürk, ÖzcanAs the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this study, we aim to make faulty chips designed with Network-on-Chip (NoC) communication usable. Specifically, we present a fault-tolerant irregular topology generation method for application specific NoC designs. Designed NoC topology allows a different routing path if there is a link failure on the default routing. We compare fault-tolerant topologies with regular fault-tolerant ring topologies, and non-fault-tolerant application specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. © 2014 IEEE.Item Open Access Fault-tolerant topology generation method for application-specific network-on-chips(Institute of Electrical and Electronics Engineers, 2015) Tosun, S.; Ajabshir, V. B.; Mercanoglu, O.; Ozturk, O.As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this paper, we aim to make faulty chips designed with network-on-chip (NoC) communication usable. Specifically, we present fault-tolerant irregular topology-generation method for application-specific NoC designs. Designed NoC topology allows different routing path if there is a link failure on the default routing path. Additionally, we present a simulated annealing-based application mapping algorithm aiming to minimize total energy consumption of the NoC design. We compare fault-tolerant topologies with nonfault-tolerant application-specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. Our results demonstrate that our method is able to determine fault-tolerant topologies with negligible area increase and better energy values.Item Open Access Heterogeneous network-on-chip design through evolutionary computing(Taylor & Francis, 2010) Ozturk, O.; Demirbas, D.This article explores the use of biologically inspired evolutionary computational techniques for designing and optimising heterogeneous network-on-chip (NoC) architectures, where the nodes of the NoC-based chip multiprocessor exhibit different properties such as performance, energy, temperature, area and communication bandwidth. Focusing primarily on array-dominated applications and heterogeneous execution environments, the proposed approach tries to optimise the distribution of the nodes for a given NoC area under the constraints present in the environment. This article is the first one, to our knowledge, that explores the possibility of employing evolutionary computational techniques for optimally placing the heterogeneous nodes in an NoC. We also compare our approach with an optimal integer linear programming (ILP) approach using a commercial ILP tool. The results collected so far are very encouraging and indicate that the proposed approach generates close results to the ILP-based approach with minimal execution latencies. © 2010 Taylor & Francis.Item Open Access An ILP formulation for application mapping onto Network-on-Chips(IEEE, 2009) Tosun, S.; Öztürk, Özcan; Ozen, M.Ever shrinking technologies in VLSI era made it possible to place several modules onto a single die. However, the need for the new communication methods has also increased dramatically since traditional bus-based systems suffer from signal propagation delays, signal integrity, and scalability. Network-on-Chip (NoC) is the biggest step towards the communication bottleneck of System-on-Chip (SoC) architectures. In this paper, we present an Integer Linear Programming (ILP) formulation for application mapping onto mesh based Network-on-Chips to minimize the energy consumption of the system. The proposed method obtains optimal or close to optimal results within the given computation time limit. We also experimentally investigate the impact of the size of the mesh architecture on the application mapping and total communication. ©2009 IEEE.Item Open Access ILP-based communication reduction for heterogeneous 3D network-on-chips(IEEE, 2013-02-03) Aktürk, İsmail; Öztürk, ÖzcanNetwork-on-Chip (NoC) architectures and three-dimensional integrated circuits (3D ICs) have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. We explore how heterogeneous processors can be mapped onto the given 3D chip area to minimize the data access costs. Our initial results indicate that the proposed approach generates promising results within tolerable solution times. © 2013 IEEE.Item Open Access OptMem: dark-silicon aware low latency hybrid memory design(IEEE, 2016-01) Onsori, Salman; Asad, Arghavan A; Raahemifar, K.; Fathy, M.In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static random access memory (SRAM) and spin-Transfer torque magnetic random-Access memory(STT-RAM) memories on the memory layer to exploit advantages of both technologies. Power consumption that is the main challenge in the dark silicon era is represented as a main constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D Chip-Multiprocessor (CMP). Experimental results show that the proposed architecture improves the energy consumption and performanceof the 3D CMPabout 25.8% and 12.9% on averagecompared to the Baseline memory design. © 2016 IEEE.Item Open Access Plasmonic gratings for enhanced near infrared sensitivity of Silicon based Schottky photodetectors(IEEE, 2011) Polat, Kazım Gürkan; Aygun, Levent Erdal; Okyay, Ali KemalSchottky photodetectors have been intensively investigated due to their high speeds, low device capacitances, and sensitivity in telecommunication standard bands, in the 0.8μm to 1.5μm wavelength range. Due to extreme cost advantage of Silicon over compound semiconductors, and seamless integration with VLSI circuits, metal-Silicon Schottky photodetectors are attractive low cost alternatives to InGaAs technology. However, efficiencies of Schottky type photodetectors are limited due to thin absorption region. Previous efforts such as resonant cavities increase the sensitivity using optical techniques, however their integration with VLSI circuits is difficult. Therefore, there is a need for increasing Schottky detector sensitivity, in a VLSI compatible fashion. To address this problem, we design plasmonic grating structures to increase light absorption at the metal-Silicon Schottky interface. There are earlier reports of plasmonic structures to increase Schottky photodetector sensitivity, with a renowned interest in the utilization of plasmonic effects to improve the absorption characteristics of metal-semiconductor interfaces. In this work, we report the design, fabrication and characterization of Gold-Silicon Schottky photodetectors with enhanced absorption in the near infrared region. © 2011 IEEE.Item Open Access Reconfigurable hardened latch and flip-flop for FPGAs(IEEE, 2017-07) Ahangari, Hamzeh; Alouani, I.; Öztürk, Özcan; Niar, S.In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices such as FPGAs. Specifically, we implement two reconfigurable storage elements that exploit a trade-off between reliability and amount of available resources. In fault prone conditions, JLatch (or JFF) is configured in such a way that four pre-selected normal static latches (or FFs) are combined together at circuit level to form one hardened storage cell. Solution focuses on transient faults such as soft errors, where we show that critical charge is increased by at least three orders of magnitude (1000X) to practically bring immunity against any Single Event Upset (SEU). If four latches inside an FPGA logic block are far enough, it can effectively cope with Multiple Bit Upsets (MBUs) as well. Additionally, provided that special transistor sizing is applied (only necessary for some latch structures), JLatch and JFF take advantage of a novel self-correcting technique to correct any single fault immediately. Our solution provides reconfigurability of reliability with negligible performance and area overhead with only one (two) extra transistor(s) per latch (FF). The delay of this technique is less than the delay of conventional TMR (Triple Modular Redundancy) technique with a majority voter at output. © 2017 IEEE.Item Open Access VLSI circuits for adaptive digital beamforming in ultrasound imaging(IEEE, 1993) Karaman, M.; Atalar, Abdullah; Köymen, HayrettinFor phased-array ultrasound imaging, alternative beamforming techniques and their VLSI circuits are studied to form a fully digital receive front-end hardware. In order to increase the timing accuracy in beamforming, a computationally efficient interpolation scheme to increase the sampling rate is examined. For adaptive beamforming, a phase aberration correction method with very low computational complexity is described. Image quality performance of the method is examined by processing the non-aberrated and aberrated phased-array experimental data sets of an ultrasound resolution phantom. A digital beamforming scheme based on receive focusing at the raster focal points is examined. The sector images of the resolution phantom, reconstructed from the phased-array experimental data by beamforming at the radial and raster focal points, are presented for comparison of the image resolution performances of the two beamforming schemes. VLSI circuits and their implementations for the proposed techniques are presented.Item Open Access Voltage island based heterogeneous NoC design through constraint programming(Pergamon Press, 2014) Demiriz, A.; Bagherzadeh, N.; Ozturk, O.This paper discusses heterogeneous Network-on-Chip (NoC) design from a Constraint Programming (CP) perspective and extends the formulation to solving Voltage-Frequency Island (VFI) problem. In general, VFI is a superior design alternative in terms of thermal constraints, power consumption as well as performance considerations. Given a Communication Task Graph (CTG) and subsequent task assignments for cores, cores are allocated to the best possible places on the chip in the first stage to minimize the overall communication cost among cores. We then solve the application scheduling problem to determine the optimum core types from a list of technological alternatives and to minimize the makespan. Moreover, an elegant CP model is proposed to solve VFI problem by mapping and grouping cores at the same time with scheduling the computation tasks as a limited capacity resource allocation model. The paper reports results based on real benchmark datasets from the literature.Item Open Access A Wired-AND Current-Mode Logic Circuit Technique in CMOS for Low-Voltage, High-Speed and Mixed-Signal VLSIC(1997) Ungan I.E.; Aşkar, M.A wired-AND current-mode logic (WCML) circuit technique in CMOS technology for low-voltage and high-speed VLSI circuits is proposed, and a WCML cell library is developed using standard 0.8 micron CMOS process. The proposed WCML technique applies the analog circuit design methodologies to the digital circuit design. The input and output logic signals are represented by current quantities. The supply current of the logic circuit is adjustable for the required logic speed and the switching noise level. The noise is reduced on the power supply lines and in the substrate by the current-steering technique and by the smooth swing of the reduced node potentials. Precise analog circuits and fast digital circuits can be integrated on the same silicon substrate by using the low noise property of the WCML. It is shown by the simulations that at low supply voltages, the WCML is faster and generates less switching noise when compared to the static-CMOS logic. At high speeds, the power dissipation of the WCML is less than that of the static-CMOS logic.