Application-specific heterogeneous network-on-chip design

Date
2014
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Source Title
The Computer Journal
Print ISSN
0010-4620
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Publisher
Oxford University Press
Volume
57
Issue
8
Pages
1117 - 1131
Language
English
Type
Article
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Abstract

As a result of increasing communication demands, application-specific and scalable Network-on-Chips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor System-on-Chips. A challenge in application-specific NoC design is to find the right balance among different tradeoffs, such as communication latency, power consumption and chip area. We propose a novel approach that generates latency-aware heterogeneous NoC topology. Experimental results show that our approach improves the total communication latency up to 27% with modest power consumption. © 2013 The Author 2013. Published by Oxford University Press on behalf of The British Computer Society.

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Keywords
Many-core architectures, Multiprocessor system-on-chip design, Network-on-chip synthesis, Computer architecture, Heterogeneous networks, Microprocessor chips, Multiprocessing systems, Routers, VLSI circuits, Chip multiprocessor, Communication latency, Heterogeneous NoC
Citation
Published Version (Please cite this version)