Heterogeneous network-on-chip design through evolutionary computing

Date
2010
Authors
Ozturk, O.
Demirbas, D.
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Instructor
Source Title
International Journal of Electronics
Print ISSN
0020-7217
Electronic ISSN
1362-3060
Publisher
Taylor & Francis
Volume
97
Issue
10
Pages
1139 - 1161
Language
English
Type
Article
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Abstract

This article explores the use of biologically inspired evolutionary computational techniques for designing and optimising heterogeneous network-on-chip (NoC) architectures, where the nodes of the NoC-based chip multiprocessor exhibit different properties such as performance, energy, temperature, area and communication bandwidth. Focusing primarily on array-dominated applications and heterogeneous execution environments, the proposed approach tries to optimise the distribution of the nodes for a given NoC area under the constraints present in the environment. This article is the first one, to our knowledge, that explores the possibility of employing evolutionary computational techniques for optimally placing the heterogeneous nodes in an NoC. We also compare our approach with an optimal integer linear programming (ILP) approach using a commercial ILP tool. The results collected so far are very encouraging and indicate that the proposed approach generates close results to the ILP-based approach with minimal execution latencies. © 2010 Taylor & Francis.

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Keywords
Evolutionary computing, Genetic algorithm, Heterogeneous, NoC, Biologically inspired, Chip multiprocessor, Communication bandwidth, Computational technique, Execution environments, Heterogeneous nodes, Integer linear programming, Network - on - chip architectures, Network - on - chip design, Heterogeneous networks, Integer programming, Microprocessor chips, Optimization, Servers, Telecommunication systems, VLSI circuits, Genetic algorithms
Citation
Published Version (Please cite this version)