Energy reduction in 3D NoCs through communication optimization

Date
2015
Authors
Ozturk, O.
Akturk I.
Kadayif I.
Tosun, S.
Advisor
Supervisor
Co-Advisor
Co-Supervisor
Instructor
Source Title
Computing : archives for scientific computing
Print ISSN
0010-485X
Electronic ISSN
Publisher
Springer Wien
Volume
97
Issue
6
Pages
593 - 609
Language
English
Type
Article
Journal Title
Journal ISSN
Volume Title
Series
Abstract

Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. Specifically, on a heterogeneous 3D NoC architecture, we explore how different types of processors can be optimally placed to minimize data access costs. Moreover, we select the optimal set of links with optimal voltage levels. The experimental results indicate significant savings in energy consumption across a wide range of values of our major simulation parameters.

Course
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Book Title
Keywords
3D, NoC, Communication, Computer architecture, Energy utilization, Network architecture, Networks (circuits), VLSI circuits, Better performance, Communication optimization, Energy, Network-on-chip architectures, NoC architectures, Simulation parameters, Three-dimensional (3D) integrated circuits, Network-on-chip
Citation
Published Version (Please cite this version)