Fault-tolerant irregular topology design method for network-on-chips

Date
2014
Advisor
Supervisor
Co-Advisor
Co-Supervisor
Instructor
Source Title
2014 17th Euromicro Conference on Digital System Design
Print ISSN
Electronic ISSN
Publisher
IEEE
Volume
Issue
Pages
631 - 634
Language
English
Type
Conference Paper
Journal Title
Journal ISSN
Volume Title
Series
Abstract

As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this study, we aim to make faulty chips designed with Network-on-Chip (NoC) communication usable. Specifically, we present a fault-tolerant irregular topology generation method for application specific NoC designs. Designed NoC topology allows a different routing path if there is a link failure on the default routing. We compare fault-tolerant topologies with regular fault-tolerant ring topologies, and non-fault-tolerant application specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. © 2014 IEEE.

Course
Other identifiers
Book Title
Keywords
Energy, Fault tolerance, Network-on-Chip, Topology, Benchmarking, Design, Distributed computer systems, Energy utilization, Fault tolerance, Fault tolerant computer systems, Microprocessor chips, Network-on-chip, Routers, Servers, Topology, VLSI circuits, Application specific, Energy, Fault-tolerant applications, Integrated circuits (ICs), Irregular topology, Multimedia benchmarks, Network-on-chip(NoC), Single-link failures, Integrated circuit design
Citation
Published Version (Please cite this version)