Browsing by Subject "Energy utilization"

Now showing 1 - 15 of 15

Open Access
Compiler-directed energy reduction using dynamic voltage scaling and voltage islands for embedded systems
(Institute of Electrical and Electronics Engineers, 2013) Ozturk, O.; Kandemir, M.; Chen G.
Addressing power and energy consumption related issues early in the system design flow ensures good design and minimizes iterations for faster turnaround time. In particular, optimizations at software level, e.g., those supported by compilers, are very important for minimizing energy consumption of embedded applications. Recent research demonstrates that voltage islands provide the flexibility to reduce power by selectively shutting down the different regions of the chip and/or running the select parts of the chip at different voltage/frequency levels. As against most of the prior work on voltage islands that mainly focused on the architecture design and IP placement related issues, this paper studies the necessary software compiler support for voltage islands. Specifically, we focus on an embedded multiprocessor architecture that supports both voltage islands and control domains within these islands, and determine how an optimizing compiler can automatically map an embedded application onto this architecture. Such an automated support is critical since it is unrealistic to expect an application programmer to reach a good mapping correlating multiple factors such as performance and energy at the same time. Our experiments with the proposed compiler support show that our approach is very effective in reducing energy consumption. The experiments also show that the energy savings we achieve are consistent across a wide range of values of our major simulation parameters. © 1968-2012 IEEE.
Open Access
Delay analysis of timer-based frame coalescing in energy efficient ethernet
(IEEE, 2013) Akar, N.
IEEE 802.3az, also known as Energy Efficient Ethernet (EEE), aims at reducing the energy consumption of an Ethernet link by placing it in sleep mode when the link is idle. Frame coalescing mechanism proposed for EEE is an effective means to increase the average idle time of the link, thus reducing the overhead stemming from sleep/wake transitions, but at the expense of increased frame delays. Therefore, it is imperative to quantify the energy-delay trade-off while employing frame coalescing. As opposed to existing delay models that focus only on the average delays, a simple but exact queuing model is introduced for timer-based frame coalescing to find the delay distribution when the frame arrival process is Poisson and frame lengths are generally distributed. An expression for average saving in power consumption is also provided.
Open Access
Energy consumption forecasting via order preserving pattern matching
(IEEE, 2014-12) Vanlı, N. Denizcan; Sayın, Muhammed O.; Yıldız, Hikmet; Göze, Tolga; Kozat, Süleyman S.
We study sequential prediction of energy consumption of actual users under a generic loss/utility function. Particularly, we try to determine whether the energy usage of the consumer will increase or decrease in the future, which can be subsequently used to optimize energy consumption. To this end, we use the energy consumption history of the users and define finite state (FS) predictors according to the relative ordering patterns of these past observations. In order to alleviate the overfitting problems, we generate equivalence classes by tying several states in a nested manner. Using the resulting equivalence classes, we obtain a doubly exponential number of different FS predictors, one among which achieves the smallest accumulated loss, hence is optimal for the prediction task. We then introduce an algorithm to achieve the performance of this FS predictor among all doubly exponential number of FS predictors with a significantly reduced computational complexity. Our approach is generic in the sense that different tying configurations and loss functions can be incorporated into our framework in a straightforward manner. We illustrate the merits of the proposed algorithm using the real life energy usage data. © 2014 IEEE.
Open Access
Energy cost model for frequent item set discovery in unstructured P2P networks
(Springer, London, 2012) Cem, E.; Demirkaya, Ender; Esiner, E.; Ozaydin, B.; Ozkasap O.
For large scale distributed systems, designing energy efficient protocols and services has become as significant as considering conventional performance criteria like scalability, reliability, fault-tolerance and security. We consider frequent item set discovery problem in this context. Although it has attracted attention due to its extensive applicability in diverse areas, there is no prior work on energy cost model for such distributed protocols. In this paper, we develop an energy cost model for frequent item set discovery in unstructured P2P networks. To the best of our knowledge, this is the first study that proposes an energy cost model for a generic peer using gossip-based communication. As a case study protocol, we use our gossip-based approach ProFID for frequent item set discovery. After developing the energy cost model, we examine the effect of protocol parameters on energy consumption using our simulation model on PeerSim and compare push-pull method of ProFID with the well-known push-based gossiping approach. Based on the analysis results, we reformulate the upper bound for the peer's energy cost. © 2012 Springer-Verlag London Limited.
Open Access
Energy reduction in 3D NoCs through communication optimization
(Springer Wien, 2015) Ozturk, O.; Akturk I.; Kadayif I.; Tosun, S.
Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. Specifically, on a heterogeneous 3D NoC architecture, we explore how different types of processors can be optimally placed to minimize data access costs. Moreover, we select the optimal set of links with optimal voltage levels. The experimental results indicate significant savings in energy consumption across a wide range of values of our major simulation parameters.
Open Access
Energy-Optimum throughput and carrier sensing rate in csma-based wireless networks
(IEEE, 2014) Koseoglu, M.; Karasan, E.
We propose a model for the energy consumption of a node as a function of its throughput in a wireless CSMA network. We first model a single-hop network, and then a multi-hop network. We show that operating the CSMA network at a high throughput is energy inefficient since unsuccessful carrier sensing attempts increase the energy consumption per transmitted bit. Operating the network at a low throughput also causes energy inefficiency because of increased sleeping duration. Achieving a balance between these two opposite operating regimes, we derive the energy-optimum carrier-sensing rate and the energy-optimum throughput which maximize the number of transmitted bits for a given energy budget. For the single-hop case, we show that the energy-optimum total throughput increases as the number of nodes sharing the channel increases. For the multi-hop case, we show that energy-optimum throughput decreases as the degree of the conflict graph corresponding to the network increases. For both cases, the energy-optimum throughput reduces as the power required for carrier-sensing increases. The energy-optimum throughput is also shown to be substantially lower than the maximum throughput and the gap increases as the degree of the conflict graph increases for multi-hop networks. © 2002-2012 IEEE.
Open Access
Energy-price-driven query processing in multi-center web search engines
(IEEE, 2011-07) Kayaaslan, Enver; Cambazoglu, B. B.; Blanco, R.; Junqueira, F. P.; Aykanat, Cevdet
Concurrently processing thousands of web queries, each with a response time under a fraction of a second, necessitates maintaining and operating massive data centers. For large-scale web search engines, this translates into high energy consumption and a huge electric bill. This work takes the challenge to reduce the electric bill of commercial web search engines operating on data centers that are geographically far apart. Based on the observation that energy prices and query workloads show high spatio-temporal variation, we propose a technique that dynamically shifts the query workload of a search engine between its data centers to reduce the electric bill. Experiments on real-life query workloads obtained from a commercial search engine show that significant financial savings can be achieved by this technique.
Open Access
Fault-tolerant irregular topology design method for network-on-chips
(IEEE, 2014) Tosun, S.; Ajabshir V.B.; Mercanoglu O.; Öztürk, Özcan
As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this study, we aim to make faulty chips designed with Network-on-Chip (NoC) communication usable. Specifically, we present a fault-tolerant irregular topology generation method for application specific NoC designs. Designed NoC topology allows a different routing path if there is a link failure on the default routing. We compare fault-tolerant topologies with regular fault-tolerant ring topologies, and non-fault-tolerant application specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. © 2014 IEEE.
Open Access
Fault-tolerant topology generation method for application-specific network-on-chips
(Institute of Electrical and Electronics Engineers, 2015) Tosun, S.; Ajabshir, V. B.; Mercanoglu, O.; Ozturk, O.
As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this paper, we aim to make faulty chips designed with network-on-chip (NoC) communication usable. Specifically, we present fault-tolerant irregular topology-generation method for application-specific NoC designs. Designed NoC topology allows different routing path if there is a link failure on the default routing path. Additionally, we present a simulated annealing-based application mapping algorithm aiming to minimize total energy consumption of the NoC design. We compare fault-tolerant topologies with nonfault-tolerant application-specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. Our results demonstrate that our method is able to determine fault-tolerant topologies with negligible area increase and better energy values.
Open Access
FPGA implementation of a fault-tolerant application-specific NoC design
(IEEE, 2016-04) Yeşil, Şerif; Tosun, S.; Öztürk, Özcan
Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem is fatal to application-specific Network-on-Chip (NoC) designs as well if they cannot tolerate such failures. One solution to this problem can be having alternative routing options on the network for each communicating pair. In this study, we present an FPGA implementation of such a method for application-specific NoCs. This method adds additional network resources to the non-fault-tolerant design in an attempt to make it fault-tolerant. We show the effects of the presented fault-tolerant method on an FPGA implementation of Mp3 encoder based on energy consumption and area increase against non-fault-tolerant case. © 2016 IEEE.
Open Access
A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors
(IEEE, 2016-05) Asad, Arghavan; Onsori, Salman; Fathy, M.; Jahed-Motlagh, M. R.; Raahemifar, K.
Main memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era cause a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies offer many desirable characteristics such as near-zero leakage power, high density and non-volatility. They can significantly mitigate the issue of memory leakage power in future embedded chip-multiprocessor (eCMP) systems. However, they suffer from challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we propose a stacked hybrid memory system for 3D chip-multiprocessors to take advantages of both traditional and non-volatile memory technologies. For reaching this target, we present a convex optimization-based model that minimizes the system energy consumption while satisfy endurance constraint in order to design a reliable memory system. Experimental results show that the proposed method improves energy-delay product (EDP) and performance by about 44.8% and 13.8% on average respectively compared with the traditional memory design where single technology is used. © 2016 IEEE.
Open Access
High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model
(IEEE, 2016-05) Onsori, Salman; Asad, Arghavan; Raahemifar, K.; Fathy, M.
In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and efficiently maps applications/threads on cores in the core layer. Power consumption that is the main challenge in the dark silicon era is represented as a power constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D CMP. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D CMP compared to the Baseline memory design. © 2016 IEEE.
Open Access
Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach
(IEEE, 2015-12) Onsori, Salman; Asad, A.; Öztürk, Özcan; Fathy, M.
Energy consumption becomes the most critical limitation on the performance of nowadays embedded system designs. On-chip memories due to major contribution in overall system energy consumption are always significant issue for embedded systems. Using conventional memory technologies in future designs in nano-scale era causes a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies are promising replacement for conventional memory structure in embedded systems due to its attractive characteristics such as near-zero leakage power, high density and non-volatility. Recent advantages of NVM technologies can significantly mitigate the issue of memory leakage power. However, they introduce new challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we propose a stacked hybrid memory system to minimize energy consumption for 3D embedded chip-multiprocessors (eCMP). For reaching this target, we present a convex optimization-based model to distribute data blocks between SRAM and NVM banks based on data access pattern derived by compiler. Our compiler-assisted hybrid memory architecture can achieve up to 51.28 times improvement in lifetime. In addition, experimental results show that our proposed method reduce energy consumption by 56% on average compared to the traditional memory design where single technology is used. © 2015 IEEE.
Open Access
A non-atochastic learning approach to energy efficient mobility management
(Institute of Electrical and Electronics Engineers Inc., 2016) Shen, C.; Tekin, C.; Van Der Schaar, M.
Energy efficient mobility management is an important problem in modern wireless networks with heterogeneous cell sizes and increased nodes densities. We show that optimization-based mobility protocols cannot achieve long-Term optimal energy consumption, particularly for ultra-dense networks (UDNs). To address the complex dynamics of UDN, we propose a non-stochastic online-learning approach, which does not make any assumption on the statistical behavior of the small base station (SBS) activities. In addition, we introduce handover cost to the overall energy consumption, which forces the resulting solution to explicitly minimize frequent handovers. The proposed batched randomization with exponential weighting (BREW) algorithm relies on batching to explore in bulk, and hence reduces unnecessary handovers. We prove that the regret of BREW is sublinear in time, thus guaranteeing its convergence to the optimal SBS selection. We further study the robustness of the BREW algorithm to delayed or missing feedback. Moreover, we study the setting where SBSs can be dynamically turned ON and OFF. We prove that sublinear regret is impossible with respect to arbitrary SBS ON/OFF, and then develop a novel learning strategy, called ranking expert (RE), that simultaneously takes into account the handover cost and the availability of SBS. To address the high complexity of RE, we propose a contextual ranking expert (CRE) algorithm that only assigns experts in a given context. Rigorous regret bounds are proved for both RE and CRE with respect to the best expert. Simulations show that not only do the proposed mobility algorithms greatly reduce the system energy consumption, but they are also robust to various dynamics which are common in practical ultra-dense wireless networks.
Open Access
OptMem: dark-silicon aware low latency hybrid memory design
(IEEE, 2016-01) Onsori, Salman; Asad, Arghavan A; Raahemifar, K.; Fathy, M.
In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static random access memory (SRAM) and spin-Transfer torque magnetic random-Access memory(STT-RAM) memories on the memory layer to exploit advantages of both technologies. Power consumption that is the main challenge in the dark silicon era is represented as a main constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D Chip-Multiprocessor (CMP). Experimental results show that the proposed architecture improves the energy consumption and performanceof the 3D CMPabout 25.8% and 12.9% on averagecompared to the Baseline memory design. © 2016 IEEE.