High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model

Date
2016-05
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Proceedings - IEEE International Symposium on Circuits and Systems, 2016
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IEEE
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2607 - 2610
Language
English
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Abstract

In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and efficiently maps applications/threads on cores in the core layer. Power consumption that is the main challenge in the dark silicon era is represented as a power constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D CMP. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D CMP compared to the Baseline memory design. © 2016 IEEE.

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