Browsing by Subject "Proposed architectures"
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Item Open Access Energy efficient IP-connectivity with IEEE 802.11 for home M2M networks(Oxford University Press, 2017) Ozcelik, I. M.; Korpeoglu, I.; Agrawala, A.Machine-to-machine communication (M2M) technology enables large-scale device communication and networking, including home devices and appliances. A critical issue for home M2M networks is how to efficiently integrate existing home consumer devices and appliances into an IP-based wireless M2M network with least modifications. Due to its popularity and widespread use in closed spaces, Wi-Fi is a good alternative as a wireless technology to enable M2M networking for home devices. This paper addresses the energy-efficient integration of home appliances into a Wi-Fi- and IP-based home M2M network. Toward this goal, we first propose an integration architecture that requires least modifications to existing components. Then, we propose a novel long-term sleep scheduling algorithm to be applied with the existing 802.11 power save mode. The proposed scheme utilizes the multicast DNS protocol to maintain device and service availability when devices go into deep sleep mode. We prototyped our proposed architecture and algorithm to build a M2M network testbed of home appliances. We performed various experiments on this testbed to evaluate the operation and energy savings of our proposal. We also did simulation experiments for larger scale scenarios. As a result of our test-bed and simulation experiments, we observed significant energy savings compared to alternatives while also ensuring device and service availability. © The British Computer Society 2017. All rights reserved.Item Open Access An FPGA implementation architecture for decoding of polar codes(IEEE, 2011) Pamuk, AlptekinPolar codes are a class of codes versatile enough to achieve the Shannon bound in a large array of source and channel coding problems. For that reason it is important to have efficient implementation architectures for polar codes in hardware. Motivated by this fact we propose a belief propagation (BP) decoder architecture for an increasingly popular hardware platform; Field Programmable Gate Array (FPGA). The proposed architecture supports any code rate and is quite flexible in terms of hardware complexity and throughput. The architecture can also be extended to support multiple block lengths without increasing the hardware complexity a lot. Moreover various schedulers can be adapted into the proposed architecture so that list decoding techniques can be used with a single block. Finally the proposed architecture is compared with a convolutional turbo code (CTC) decoder for WiMAX taken from a Xilinx Product Specification and seen that polar codes are superior to CTC codes both in hardware complexity and throughput. © 2011 IEEE.Item Open Access Graph analytics accelerators for cognitive systems(Institute of Electrical and Electronics Engineers, 2017) Ozdal, M. M.; Yesil, S.; Kim, T.; Ayupov, A.; Greth, J.; Burns, S.; Ozturk, O.Hardware accelerators are known to be performance and power efficient. This article focuses on accelerator design for graph analytics applications, which are commonly used kernels for cognitive systems. The authors propose a templatized architecture that is specifically optimized for vertex-centric graph applications with irregular memory access patterns, asynchronous execution, and asymmetric convergence. The proposed architecture addresses the limitations of existing CPU and GPU systems while providing a customizable template. The authors' experiments show that the generated accelerators can outperform a high-end CPU system with up to 3 times better performance and 65 times better power efficiency. © 1981-2012 IEEE.Item Open Access High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model(IEEE, 2016-05) Onsori, Salman; Asad, Arghavan; Raahemifar, K.; Fathy, M.In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and efficiently maps applications/threads on cores in the core layer. Power consumption that is the main challenge in the dark silicon era is represented as a power constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D CMP. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D CMP compared to the Baseline memory design. © 2016 IEEE.Item Open Access A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model(IEEE, 2015-11) Onsori, Salman; Asad, Arghavan; Raahemifar, K.; Fathy, M.In this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and maps applications/threads on cores in the core layer effectively. The detailed proposed model satisfies the power constraint which is the main challenge of dark-silicon era. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D eCMP compared to the Baseline memory design. © 2015 IEEE.Item Open Access A two phase successive cancellation decoder architecture for polar codes(IEEE, 2013) Pamuk, Alptekin; Arıkan, ErdalWe propose a two-phase successive cancellation (TPSC) decoder architecture for polar codes that exploits the array-code property of polar codes by breaking the decoding of a length-TV polar code into a series of length-√ L decoding cycles. Each decoding cycle consists of two phases: a first phase for decoding along the columns and a second phase for decoding along the rows of the code array. The reduced decoder size makes it more affordable to implement the core decoder logic using distributed memory elements consisting of flip-flops (FFs), as opposed to slower random access memory (RAM), leading to a speed up in clock frequency. To minimize the circuit complexity, a single decoder unit is used in both phases with minor modifications. The re-use of the same decoder module makes it necessary to recall certain internal decoder state variables between decoding cycles. Instead of storing the decoder state variables in RAM, the decoder discards them and calculates them again when needed. Overall, the decoder has O(√ L) circuit complexity excluding RAM, and a latency of approximately 2.57V. A RAM of size O(N) is needed for storing the channel log-likelihood variables and the decoder decision variables. As an example of the proposed method, a length N = 214 bit polar code is implemented in an FPGA and the synthesis results are compared with a previously reported FPGA implementation. The results show that the proposed architecture has lower complexity, lower memory utilization with higher throughput, and a clock frequency that is less sensitive to code length. © 2013 IEEE.