A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model
Date
2015-11
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Source Title
ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)
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Publisher
IEEE
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Pages
261 - 262
Language
English
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Abstract
In this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and maps applications/threads on cores in the core layer effectively. The detailed proposed model satisfies the power constraint which is the main challenge of dark-silicon era. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D eCMP compared to the Baseline memory design. © 2015 IEEE.
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Keywords
Convex-optimization , Embedded chip-multiprocessor (eCMP) , Hybrid memory architecture , Non-volatile memory (NVM) , Adaptive systems , Convex optimization , Data storage equipment , Design , Digital storage , Multiprocessing systems , Optimization , Product design , Programmable logic controllers , Random access storage , Static random access storage , Convex modeling , Embedded chips , Energy delay product , Memory design , Memory layers , Non-volatile memory , Power constraints , Proposed architectures , Memory architecture