Browsing by Subject "Non-volatile memory"

Now showing 1 - 6 of 6

Open Access
A heterogeneous memory organization with minimum energy consumption in 3D chip-multiprocessors
(IEEE, 2016-05) Asad, Arghavan; Onsori, Salman; Fathy, M.; Jahed-Motlagh, M. R.; Raahemifar, K.
Main memories play an important role in overall energy consumption of embedded systems. Using conventional memory technologies in future designs in nanoscale era cause a drastic increase in leakage power consumption and temperature-related problems. Emerging non-volatile memory (NVM) technologies offer many desirable characteristics such as near-zero leakage power, high density and non-volatility. They can significantly mitigate the issue of memory leakage power in future embedded chip-multiprocessor (eCMP) systems. However, they suffer from challenges such as limited write endurance and high write energy consumption which restrict them for adoption in modern memory systems. In this article, we propose a stacked hybrid memory system for 3D chip-multiprocessors to take advantages of both traditional and non-volatile memory technologies. For reaching this target, we present a convex optimization-based model that minimizes the system energy consumption while satisfy endurance constraint in order to design a reliable memory system. Experimental results show that the proposed method improves energy-delay product (EDP) and performance by about 44.8% and 13.8% on average respectively compared with the traditional memory design where single technology is used. © 2016 IEEE.
Open Access
High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model
(IEEE, 2016-05) Onsori, Salman; Asad, Arghavan; Raahemifar, K.; Fathy, M.
In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and efficiently maps applications/threads on cores in the core layer. Power consumption that is the main challenge in the dark silicon era is represented as a power constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D CMP. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D CMP compared to the Baseline memory design. © 2016 IEEE.
Open Access
A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model
(IEEE, 2015-11) Onsori, Salman; Asad, Arghavan; Raahemifar, K.; Fathy, M.
In this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and maps applications/threads on cores in the core layer effectively. The detailed proposed model satisfies the power constraint which is the main challenge of dark-silicon era. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D eCMP compared to the Baseline memory design. © 2015 IEEE.
Open Access
Implications of non-volatile memory as primary storage for database management systems
(IEEE, 2017) Mustafa, Naveed Ul; Armejach, A.; Öztürk, Özcan; Cristal, A.; Unsal, O. S.
Traditional Database Management System (DBMS) software relies on hard disks for storing relational data. Hard disks are cheap, persistent, and offer huge storage capacities. However, data retrieval latency for hard disks is extremely high. To hide this latency, DRAM is used as an intermediate storage. DRAM is significantly faster than disk, but deployed in smaller capacities due to cost and power constraints, and without the necessary persistency feature that disks have. Non-Volatile Memory (NVM) is an emerging storage class technology which promises the best of both worlds. It can offer large storage capacities, due to better scaling and cost metrics than DRAM, and is non-volatile (persistent) like hard disks. At the same time, its data retrieval time is much lower than that of hard disks and it is also byte-addressable like DRAM. In this paper, we explore the implications of employing NVM as primary storage for DBMS. In other words, we investigate the modifications necessary to be applied on a traditional relational DBMS to take advantage of NVM features. As a case study, we have modified the storage engine (SE) of PostgreSQL enabling efficient use of NVM hardware. We detail the necessary changes and challenges such modifications entail and evaluate them using a comprehensive emulation platform. Results indicate that our modified SE reduces query execution time by up to 40% and 14.4% when compared to disk and NVM storage, with average reductions of 20.5% and 4.5%, respectively. © 2016 IEEE.
Open Access
Novel materials for thin-film memory cells
(2014) Çimen, Furkan
The tremendous growth in consumer electronics market increased the need for low-cost, low-power and high quality memory chips. This challenge is further aggravated by the continuous increase in density and scaling of the gate length, since it creates a major challenge for current nonvolatile flash memory devices to maintain reliability and retention. Therefore, it is imperative to find new materials and novel fabrication processes to be incorporated in memory cells in order to keep up with the enormous rate of increase in consumer needs. In the first part of this thesis, we demonstrate a charge trapping memory with graphene nanoplatelets embedded in atomic layer deposited ZnO. We first introduce the fabrication process for the memory device and then investigate the memory characteristics. Our experimental analysis on the memory cell shows a large threshold voltage Vt shift (4V ) at low operating voltages (6/ − 6V ), good retention (> 10 years), and good endurance characteristics (> 104 cycles). The resulting memory behavior is also verified by theoretical computations. In the second part, we demonstrate the use of laser-synthesized indium-nitride nanoparticles (InN-NPs) as the charge trapping layer in the memory cell. We first introduce the indium-nitride nanoparticle synthesis and then detail the fabrication process of the memory device. The experimental analysis of the memory cell results in a noticeable threshold voltage Vt shift (2V ) at low operating voltages (4V ) in addition to the similar retention and endurance performance with the graphene-based memory cells. The memory behavior was also verified with theoretical computations for the InN-NPs based memory cells. In the last part of this thesis, we demonstrate a memory device with a gate stack fabricated in a single ALD step. Single-step all-ALD approach avoids the risk of contamination and incorporation of impurities in the gate stack. It also allows low-cost production by eliminating multiple equipment utilization. Motivated by these, we first present the fabrication process of the memory device and then explain the experimental and theoretical characterization and analysis. The memory effect of the thin-film ZnO charge-trapping memory cell is verified by a 2.35V hysteresis in drain current vs. gate voltage curve. The resulting memory behavior is also verified by physics-based TCAD simulations.
Open Access
OptMem: dark-silicon aware low latency hybrid memory design
(IEEE, 2016-01) Onsori, Salman; Asad, Arghavan A; Raahemifar, K.; Fathy, M.
In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static random access memory (SRAM) and spin-Transfer torque magnetic random-Access memory(STT-RAM) memories on the memory layer to exploit advantages of both technologies. Power consumption that is the main challenge in the dark silicon era is represented as a main constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D Chip-Multiprocessor (CMP). Experimental results show that the proposed architecture improves the energy consumption and performanceof the 3D CMPabout 25.8% and 12.9% on averagecompared to the Baseline memory design. © 2016 IEEE.