Browsing by Subject "Application specific"

Filter results by typing the first few letters
Now showing 1 - 5 of 5
  • Thumbnail Image
    ItemOpen Access
    Çizge uygulamalarına özel işlemci tasarımı
    (IEEE, 2022-08-29) Pulat, Gülce; Saeed, Aamir; Yenimol, Mehmetali Semi; Gülgeç, Utku; Öztürk, Özcan
    Bir çok büyük veri işleme uygulaması “PageRank”, “İşbirliğine Dayalı Filtreleme” ve “Betweenness Centrality” gibi düzensiz ve yinelemeli çizge algoritmalarından yararlanmaktadır. Çizge yapılarında her bir düğüm bir kişiye ya da nesneye karşılık gelirken, her bir ayrıt da bir kişi ya da nesne çifti arasındaki ilişkiye karşılık gelmektedir. Böylesi büyük verileri işleyen algoritmaları yürütecek genel amaçlı işlemciler yetersiz kalabilmektedir. Özellikle, güç kısıtları sebebiyle işlemci alt parçalarından sadece bir kısmı aynı anda aktif olarak kullanılabilmektedir. Bu da işlemcinin etkin olarak kullanılmasına engel olarak aktif olmayan “karanlık silikon”lar ortaya çıkarmaktadır. Bu bildirinin amacı da büyük verili ve düzensiz çizge uygulamalarını hızlı, verimli ve kolay programlanabilir biçimde çalıştıracak bir işlemci mimarisi tasarlamaktır. Literatürde çizge uygulamaları için daha önce sunulmuş çalışmalar çoğunlukla sadece yazılım ya da hızlandırıcı seviyesindedir. İşlemci seviyesi tasarımlar ise donanımsal maliyet, talep ettikleri mimari destek ve komut seti değişiklikleri açılarından bu bildiri kapsamında tanıtılacak işlemciden farklıdır.
  • Thumbnail Image
    ItemOpen Access
    Fault-tolerant irregular topology design method for network-on-chips
    (IEEE, 2014) Tosun, S.; Ajabshir V.B.; Mercanoglu O.; Öztürk, Özcan
    As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this study, we aim to make faulty chips designed with Network-on-Chip (NoC) communication usable. Specifically, we present a fault-tolerant irregular topology generation method for application specific NoC designs. Designed NoC topology allows a different routing path if there is a link failure on the default routing. We compare fault-tolerant topologies with regular fault-tolerant ring topologies, and non-fault-tolerant application specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. © 2014 IEEE.
  • Thumbnail Image
    ItemOpen Access
    Fault-tolerant topology generation method for application-specific network-on-chips
    (Institute of Electrical and Electronics Engineers, 2015) Tosun, S.; Ajabshir, V. B.; Mercanoglu, O.; Ozturk, O.
    As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this paper, we aim to make faulty chips designed with network-on-chip (NoC) communication usable. Specifically, we present fault-tolerant irregular topology-generation method for application-specific NoC designs. Designed NoC topology allows different routing path if there is a link failure on the default routing path. Additionally, we present a simulated annealing-based application mapping algorithm aiming to minimize total energy consumption of the NoC design. We compare fault-tolerant topologies with nonfault-tolerant application-specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. Our results demonstrate that our method is able to determine fault-tolerant topologies with negligible area increase and better energy values.
  • Thumbnail Image
    ItemOpen Access
    FPGA implementation of a fault-tolerant application-specific NoC design
    (IEEE, 2016-04) Yeşil, Şerif; Tosun, S.; Öztürk, Özcan
    Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem is fatal to application-specific Network-on-Chip (NoC) designs as well if they cannot tolerate such failures. One solution to this problem can be having alternative routing options on the network for each communicating pair. In this study, we present an FPGA implementation of such a method for application-specific NoCs. This method adds additional network resources to the non-fault-tolerant design in an attempt to make it fault-tolerant. We show the effects of the presented fault-tolerant method on an FPGA implementation of Mp3 encoder based on energy consumption and area increase against non-fault-tolerant case. © 2016 IEEE.
  • Thumbnail Image
    ItemOpen Access
    Hardware accelerator design for data centers
    (IEEE, 2016-11) Yeşil, Şerif; Özdal, Muhammet Mustafa; Kim, T.; Ayupov, A.; Burns, S.; Öztürk, Özcan.
    As the size of available data is increasing, it is becoming inefficient to scale the computational power of traditional systems. To overcome this problem, customized application-specific accelerators are becoming integral parts of modern system on chip (SOC) architectures. In this paper, we summarize existing hardware accelerators for data centers and discuss the techniques to implement and embed them along with the existing SOCs. © 2015 IEEE.