Thin-film ZnO charge-trapping memory cell grown in a single ALD step
buir.contributor.author | Okyay, Ali Kemal | |
dc.citation.epage | 1716 | en_US |
dc.citation.issueNumber | 12 | en_US |
dc.citation.spage | 1714 | en_US |
dc.citation.volumeNumber | 33 | en_US |
dc.contributor.author | Oruc, F. B. | en_US |
dc.contributor.author | Cimen, F. | en_US |
dc.contributor.author | Rizk, A. | en_US |
dc.contributor.author | Ghaffari, M. | en_US |
dc.contributor.author | Nayfeh, A. | en_US |
dc.contributor.author | Okyay, Ali Kemal | en_US |
dc.date.accessioned | 2016-02-08T09:43:43Z | |
dc.date.available | 2016-02-08T09:43:43Z | |
dc.date.issued | 2012-10-26 | en_US |
dc.department | Department of Electrical and Electronics Engineering | en_US |
dc.department | Institute of Materials Science and Nanotechnology (UNAM) | en_US |
dc.description.abstract | A thin-film ZnO-based single-transistor memory cell with a gate stack deposited in a single atomic layer deposition step is demonstrated. Thin-film ZnO is used as channel material and charge-trapping layer for the first time. The extracted mobility and subthreshold slope of the thin-film device are 23 cm2/V · s and 720 mV/dec, respectively. The memory effect is verified by a 2.35-V hysteresis in the $I\rm drain- $V\rm gate curve. Physics-based TCAD simulations show very good agreement with the experimental results providing insight to the charge-trapping physics. | en_US |
dc.description.provenance | Made available in DSpace on 2016-02-08T09:43:43Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 70227 bytes, checksum: 26e812c6f5156f83f0e77b261a471b5a (MD5) Previous issue date: 2012 | en |
dc.identifier.doi | 10.1109/LED.2012.2219493 | en_US |
dc.identifier.issn | 0741-3106 | |
dc.identifier.uri | http://hdl.handle.net/11693/21253 | |
dc.language.iso | English | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/LED.2012.2219493 | en_US |
dc.source.title | IEEE Electron Device Letters | en_US |
dc.subject | Atomic layer deposition (ALD) | en_US |
dc.subject | Flash memory | en_US |
dc.subject | Thin-film transistor (TFT) | en_US |
dc.subject | ZnO | en_US |
dc.subject | Channel materials | en_US |
dc.subject | Charge trapping memories | en_US |
dc.subject | Gate stacks | en_US |
dc.subject | Memory cell | en_US |
dc.subject | Memory effects | en_US |
dc.subject | Physics-based | en_US |
dc.subject | Subthreshold slope | en_US |
dc.subject | TCAD simulation | en_US |
dc.subject | Thin-film transistor (TFTs) | en_US |
dc.subject | ZnO | en_US |
dc.subject | Atomic layer deposition | en_US |
dc.subject | Flash memory | en_US |
dc.subject | Semiconductor storage | en_US |
dc.subject | Thin film devices | en_US |
dc.subject | Zinc oxide | en_US |
dc.subject | Thin film transistors | en_US |
dc.title | Thin-film ZnO charge-trapping memory cell grown in a single ALD step | en_US |
dc.type | Article | en_US |
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