Laser lithography of monolithically-integrated multi-level microchannels in silicon

Abstract

The trend toward ever-increased speeds for microelectronics is challenged bythe emergence of heat-wall, leading to the faltering of Moore’s Law. Apotential solution may be integrating microfluidic channels into silicon (Si), todeliver controlled amounts of cooling fluid and regulate hot spots. Suchmeandering microfluidic channels within other transparent materials alreadyplayed significant roles, including in biomedical and sensor applications;however, analogous channel architectures do not exist in Si. Here, a novelmethod is proposed to fabricate buried microchannel arrays monolithicallyintegrated into Si, without altering the wafer surface. A two-step,laser-assisted subtractive removal method is exploited, enabling fully-buriedmulti-level architectures, with control on the channel port geometry, depth,curvature, and aspect ratio. The selective removal rate is 750 μm per h perchannel, and the channel inner-wall roughness is 230 nm. The methodpreserves top wafer surface roughness of 2 nm, with significant potential for3D integrated systems.