Browsing by Subject "Reconfigurable hardware"

Now showing 1 - 7 of 7

Open Access
Design and fabrication of CSWAP gate based on nano-electromechanical systems
(Springer, Cham, 2016) Yüksel, Mert; Erbil, Selçuk Oğuz; Arı, Atakan B.; Hanay, M. Selim
In order to reduce undesired heat dissipation, reversible logic offers a promising solution where the erasure of information can be avoided to overcome the Landauer limit. Among the reversible logic gates, Fredkin (CSWAP) gate can be used to compute any Boolean function in a reversible manner. To realize reversible computation gates, Nano-electromechanical Systems (NEMS) offer a viable platform, since NEMS can be produced en masse using microfabrication technology and controlled electronically at high-speeds. In this work-in-progress paper, design and fabrication of a NEMS-based implementation of a CSWAP gate is presented. In the design, the binary information is stored by the buckling direction of nanomechanical beams and CSWAP operation is accomplished through a mechanism which can selectively allow/block the forces from input stages to the output stages. The gate design is realized by fabricating NEMS devices on a Silicon-on-Insulator substrate. © Springer International Publishing Switzerland 2016.
Open Access
Enhanced tunability of V-shaped plasmonic structures using ionic liquid gating and graphene
(Elsevier Ltd, 2016) Ozdemir, O.; Aygar, A. M.; Balci, O.; Kocabas, C.; Caglayan, H.; Özbay, Ekmel
Graphene is a strong candidate for active optoelectronic devices because of its electrostatically tunable optical response. Current substrate back-gating methods are unable to sustain high fields through graphene unless a high gate voltage is applied. In order to solve this problem, ionic liquid gating is used which allows substrate front side gating, thus eliminating the major loss factors such as a dielectric layer and a thick substrate layer. On the other hand, due to its two dimensional nature, graphene interacts weakly with light and this interaction limits its efficiency in optoelectronic devices. However, V-shaped plasmonic antennas can be used to enhance the incident electric field intensity and confine the electric field near graphene thus allowing further interaction with graphene. Combining V-shaped nanoantennas with the tunable response of graphene, the operation wavelength of the devices that utilize V-shaped antennas can be tuned in situ. In the present paper, we demonstrate a graphene-based device with ionic liquid gating and V- shaped plasmonic antennas to both enhance and more effectively tune the total optical response. We are able to tune the transmission response of the device for up to 389 nm by changing the gate voltage by 3.8 V in the mid-infrared regime.
Open Access
FPGA implementation of a fault-tolerant application-specific NoC design
(IEEE, 2016-04) Yeşil, Şerif; Tosun, S.; Öztürk, Özcan
Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem is fatal to application-specific Network-on-Chip (NoC) designs as well if they cannot tolerate such failures. One solution to this problem can be having alternative routing options on the network for each communicating pair. In this study, we present an FPGA implementation of such a method for application-specific NoCs. This method adds additional network resources to the non-fault-tolerant design in an attempt to make it fault-tolerant. We show the effects of the presented fault-tolerant method on an FPGA implementation of Mp3 encoder based on energy consumption and area increase against non-fault-tolerant case. © 2016 IEEE.
Open Access
Hardware accelerator design for data centers
(IEEE, 2016-11) Yeşil, Şerif; Özdal, Muhammet Mustafa; Kim, T.; Ayupov, A.; Burns, S.; Öztürk, Özcan.
As the size of available data is increasing, it is becoming inefficient to scale the computational power of traditional systems. To overcome this problem, customized application-specific accelerators are becoming integral parts of modern system on chip (SOC) architectures. In this paper, we summarize existing hardware accelerators for data centers and discuss the techniques to implement and embed them along with the existing SOCs. © 2015 IEEE.
Open Access
High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model
(IEEE, 2016-05) Onsori, Salman; Asad, Arghavan; Raahemifar, K.; Fathy, M.
In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and efficiently maps applications/threads on cores in the core layer. Power consumption that is the main challenge in the dark silicon era is represented as a power constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D CMP. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D CMP compared to the Baseline memory design. © 2016 IEEE.
Open Access
Observation of gate-tunable coherent perfect absorption of terahertz radiation in graphene
(American Chemical Society, 2016) Kakenov, N.; Balci, O.; Takan, T.; Ozkan, V. A.; Altan, H.; Kocabas, C.
We report experimental observation of electrically tunable coherent perfect absorption (CPA) of terahertz (THz) radiation in graphene. We develop a reflection-type tunable THz cavity formed by a large-area graphene layer, a metallic reflective electrode, and an electrolytic medium in between. Ionic gating in the THz cavity allows us to tune the Fermi energy of graphene up to 1 eV and to achieve a critical coupling condition at 2.8 THz with absorption of 99%. With the enhanced THz absorption, we were able to measure the Fermi energy dependence of the transport scattering time of highly doped graphene. Furthermore, we demonstrate flexible active THz surfaces that yield large modulation in the THz reflectivity with low insertion losses. We anticipate that the gate-tunable CPA will lead to efficient active THz optoelectronics applications.
Open Access
Reconfigurable hardened latch and flip-flop for FPGAs
(IEEE, 2017-07) Ahangari, Hamzeh; Alouani, I.; Öztürk, Özcan; Niar, S.
In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices such as FPGAs. Specifically, we implement two reconfigurable storage elements that exploit a trade-off between reliability and amount of available resources. In fault prone conditions, JLatch (or JFF) is configured in such a way that four pre-selected normal static latches (or FFs) are combined together at circuit level to form one hardened storage cell. Solution focuses on transient faults such as soft errors, where we show that critical charge is increased by at least three orders of magnitude (1000X) to practically bring immunity against any Single Event Upset (SEU). If four latches inside an FPGA logic block are far enough, it can effectively cope with Multiple Bit Upsets (MBUs) as well. Additionally, provided that special transistor sizing is applied (only necessary for some latch structures), JLatch and JFF take advantage of a novel self-correcting technique to correct any single fault immediately. Our solution provides reconfigurability of reliability with negligible performance and area overhead with only one (two) extra transistor(s) per latch (FF). The delay of this technique is less than the delay of conventional TMR (Triple Modular Redundancy) technique with a majority voter at output. © 2017 IEEE.