Browsing by Subject "MOS devices"
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Item Open Access Electrical characteristics of β-Ga2O3 thin films grown by PEALD(Elsevier, 2014) Altuntas, H.; Donmez, I.; Ozgit Akgun, C.; Bıyıklı, NecmiIn this work, 7.5 nm Ga2O3 dielectric thin films have been deposited on p-type (1 1 1) silicon wafer using plasma enhanced atomic layer deposition (PEALD) technique. After the deposition, Ga2O 3 thin films were annealed under N2 ambient at 600, 700, and 800 C to obtain β-phase. The structure and microstructure of the β-Ga2O3 thin films was carried out by using grazing-incidence X-ray diffraction (GIXRD). To show effect of annealing temperature on the microstructure of β-Ga2O3 thin films, average crystallite size was obtained from the full width at half maximum (FWHM) of Bragg lines using the Scherrer formula. It was found that crystallite size increased with increasing annealing temperature and changed from 0.8 nm to 9.1 nm with annealing. In order to perform electrical characterization on the deposited films, Al/β-Ga2O3/p-Si metal-oxide- semiconductor (MOS) type Schottky barrier diodes (SBDs) were fabricated using the β-Ga2O3 thin films were annealed at 800 C. The main electrical parameters such as leakage current level, reverse breakdown voltage, series resistance (RS), ideality factor (n), zero-bias barrier height (Bo), and interface states (NSS) were obtained from the current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The RS values were calculated by using Cheung methods. The energy density distribution profile of the interface states as a function of (ESS-EV) was obtained from the forward bias I-V measurements by taking bias dependence of ideality factor, effective barrier height (e), and RS into account. Also using the Norde function and C-V technique, e values were calculated and cross-checked. Results show that β-Ga2O3 thin films deposited by PEALD technique at low temperatures can be used as oxide layer for MOS devices and electrical properties of these devices are influenced by some important parameters such as NSS, RS, and β-Ga2O3 oxide layer.Item Open Access Enhanced non-volatile memory characteristics with quattro-layer graphene nanoplatelets vs. 2.85-nm Si nanoparticles with asymmetric Al2O3/HfO2 tunnel oxide(Springer New York LLC, 2015) El-Atab, N.; Turgut, B. B.; Okyay, Ali Kemal; Nayfeh, M.; Nayfeh, A.In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al2O3/HfO2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al2O3/HfO2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics.Item Open Access Memory effect by charging of ultra‐small 2‐nm laser‐synthesized solution processable Si‐nanoparticles embedded in Si–Al2O3–SiO2 structure(Wiley-VCH Verlag, 2015) El-Atab, N.; Rizk, A.; Tekcan, B.; Alkis, S.; Okyay, Ali Kemal; Nayfeh, A.A memory structure containing ultra-small 2-nm laser-synthesized silicon nanoparticles is demonstrated. The Si-nanoparticles are embedded between an atomic layer deposited high-κ dielectric Al2O3 layer and a sputtered SiO2 layer. A memory effect due to charging of the Si nanoparticles is observed using high frequency C-V measurements. The shift of the threshold voltage obtained from the hysteresis measurements is around 3.3V at 10/-10V gate voltage sweeping. The analysis of the energy band diagram of the memory structure and the negative shift of the programmed C-V curve indicate that holes are tunneling from p-type Si via Fowler-Nordheim tunneling and are being trapped in the Si nanoparticles. In addition, the structures show good endurance characteristic (>105program/erase cycles) and long retention time (>10 years), which make them promising for applications in non-volatile memory devices. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.Item Open Access Metal-semiconductor-metal ultraviolet photodetectors based on gallium nitride grown by atomic layer deposition at low temperatures(SPIE, 2014) Tekcan, B.; Ozgit Akgun, C.; Bolat, S.; Bıyıklı, Necmi; Okyay, Ali KemalProof-of-concept, first metal-semiconductor-metal ultraviolet photodetectors based on nanocrystalline gallium nitride (GaN) layers grown by low-temperature hollow-cathode plasma-assisted atomic layer deposition are demonstrated. Electrical and optical characteristics of the fabricated devices are investigated. Dark current values as low as 14 pA at a 30 V reverse bias are obtained. Fabricated devices exhibit a 15× UV/VIS rejection ratio based on photoresponsivity values at 200 nm (UV) and 390 nm (VIS) wavelengths. These devices can offer a promising alternative for flexible optoelectronics and the complementary metal oxide semiconductor integration of such devices. © 2014 Society of Photo-Optical Instrumentation Engineers (SPIE).Item Open Access Self-assembled peptide nanofiber templated ALD growth of TiO2 and ZnO semiconductor nanonetworks(Wiley - V C H Verlag GmbH & Co. KGaA, 2016) Garifullin, R.; Eren, H.; Ulusoy, T. G.; Okyay, Ali Kemal; Bıyıklı, Necmi; Güler, Mustafa O.Here peptide amphiphile (PA) nanofiber network is exploited as a three‐dimensional soft template to construct anatase TiO2 and wurtzite ZnO nanonetworks. Atomic layer deposition (ALD) technique is used to coat the organic nanonetwork template with TiO2and ZnO. ALD method enables uniform and conformal coatings with precisely controlled TiO2 and ZnO thickness. The resulting semiconducting metal oxide nanonetworks are utilized as anodic materials in dye‐sensitized solar cells. Effect of metal oxide layer thickness on device performance is studied. The devices based on thin TiO2 coatings (<10 nm) demonstrate considerable dependence on material thickness, whereas thicker (>17 nm) ZnO‐based devices do not show an explicit correlation.Item Open Access Time-resolved XPS analysis of the SiO2/Si system in the millisecond range(2004) Demirok, U. K.; Ertas, G.; Süzer, ŞefikBy applying voltage pulses to the sample rod while recording the spectrum, we show, for the first time, that it is possible to obtain a time-resolved XPS spectrum in the millisecond range. The Si 2p spectrum of a silicon sample containing a ca. 400-nm oxide layer displays a time-dependent charging shift of ca. 1.7 eV with respect to the Au 4f peaks of a gold metal strip in contact with the sample. When gold is deposited as C12-thiol-capped nanoclusters onto the same sample, this time the Au 4f peaks also display time-dependent charging behavior that is slightly different from that of the Si 2p peak. This charging/discharging is related to emptying/filling of the hole traps in the oxide layer by the stray electrons within the vacuum system guided by the external voltage pulses applied to the sample rod, which can be used to extract important parameter(s) related to the dielectric properties of surface structures.Item Open Access Two-nanometer laser synthesized Si-nanoparticles for low power memory applications(Springer International Publishing, 2016) El-Atab, N.; Okyay, Ali Kemal; Nayfeh, A.Current flash memory devices are expected to face two major challenges in the near future: density and voltage scaling. The density of the memory is related to the gate length scaling which is constrained by the gate stack, namely, the tunnel oxide thickness. In fact, the gate length is required to be commensurate with the gate stack in order to maintain a good gate control and to avoid short channel effects. However, in conventional flash memories, the tunnel oxide thickness has a lower limit of 6-7 nm (depending on NOR or NAND structure) in order to avoid back-tunneling and thus leakage of charges which destroys the necessary retention characteristic of the memory (>10 years). The second problem which needs to be solved is the high program and erase operating voltages. Once again, the limitation to operating voltage scaling is the inability to reduce gate stack thickness. Therefore, it is imperative to find novel structures and materials to be incorporated in the memory cells which would allow tunnel oxide and voltage scaling. In this study, MOSFET- and MOSCAP-based memory devices are investigated along with the use of 2-nm silicon nanoparticles (Si-NPs) for charge storage. Atomic layer deposition is used to deposit the active layer of the memory and the spin coating is performed to deliver the Si-nanoparticles across the sample.