Browsing by Subject "Flash memory"
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Item Open Access Comparison of electron and hole charge-discharge dynamics in germanium nanocrystal flash memories(AIP Publishing, 2008-02) Akça, İmran B.; Dâna, Aykutlu; Aydınlı, Atilla; Turan, R.Electron and hole charge and discharge dynamics are studied on plasma enhanced chemical vapor deposition grown metal-oxide-silicon germanium nanocrystal flash memory devices. Electron and hole charge and discharge currents are observed to differ significantly and depend on annealing conditions chosen for the formation of nanocrystals. At low annealing temperatures, holes are seen to charge slower but to escape faster than electrons. They discharge slower than electrons when annealing temperatures are raised. The results suggest that discharge currents are dominated by the interface layer acting as a quantum well for holes and by direct tunneling for elec-trons.Item Open Access Enhanced non-volatile memory characteristics with quattro-layer graphene nanoplatelets vs. 2.85-nm Si nanoparticles with asymmetric Al2O3/HfO2 tunnel oxide(Springer New York LLC, 2015) El-Atab, N.; Turgut, B. B.; Okyay, Ali Kemal; Nayfeh, M.; Nayfeh, A.In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al2O3/HfO2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al2O3/HfO2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics.Item Open Access High performance floating gate memories using graphene as charge storage medium and atomic layer deposited high-k dielectric layers as tunnel barrier(2013) Kocaay, DenizWith the ongoing development in portable electronic devices, low power consumption, improved data retention rate and higher operation speed are the merits demanded by modern non-volatile memory technology. Flash memory devices with discrete charge-trapping media are regarded as an alternative solution to conventional floating gate technology. Flash memories utilizing Sinitride as charge storage media dominate due to enhanced endurance, better scaling capability and simple fabrication. The use of high-k dielectrics as tunnel layer and control layer is also crucial in charge-trap flash memory devices since they allow further scaling and enhanced charge injection without data retention degradation. Atomic layer deposition (ALD) is a powerful technique for the growth of pinhole-free high-k dielectrics with precisely controlled thickness and high conformality. The application of graphene as charge trapping medium in flash memory devices is promising to obtain improved charge storage capability with miniaturization. Graphene acts as an effective charge storage medium due to high density of states in deep energy levels. In this thesis, we fabricate graphene flash memory devices with ALD-grown HfO2/AlN as tunnel layer and Al2O3 as control layer. Graphene oxide nanosheets are derived from the acid exfoliation of natural graphite by Hummers Method. The graphene layer is obtained by spin-coating of water soluble graphene oxide suspension followed by a thermal annealing process. Memory performance including hysteresis window, data retention rate and program transient characteristics for both electron and hole storage mechanisms are determined by performing high frequency capacitance-voltage measurements. For comparing the memory effect of graphene on device performance, we also fabricate and characterize identical flash capacitors with Si-rich SiN layer as charge storage medium and HfO2 as tunnel oxide layer. The Si-nitride films are deposited with high SiH4/NH3 gas flow ratio by plasma-enhanced chemical vapor deposition system. Graphene flash memory devices exhibit superior memory performance. Compared with Si-nitride based cells, hysteresis window, retention performance and programming speed are both significantly enhanced with the use of graphene. For electron storage, graphene flash memory provides a saturated flat band shift of 1.2 V at a write-pulse duration of 100 ns with a voltage bias of 5 V. The high density of states and high work function of graphene improve the memory performance, leading to increased charge storage capability, enhanced retention rate and faster programming operation at low voltages. The use of graphene as charge storage medium and ALD-grown high-k dielectrics as tunnel and control layers improves the existing flash technology and satisfies the requirements including scalability, at least 10-year retention, low voltage operation, faster write performance and CMOS-compatible fabrication.Item Open Access Matrix density effect on morphology of germanium nanocrystals embedded in silicon dioxide thin films(Materials Research Society, 2011) Alagoz, A. S.; Genisel, M. F.; Foss, Steinar; Finstad, T. G.; Turan, R.Flash type electronic memories are the preferred format in code storage at complex programs running on fast processors and larger media files in portable electronics due to fast write/read operations, long rewrite life, high density and low cost of fabrication. Scaling limitations of top-down fabrication approaches can be overcome in next generation flash memories by replacing continuous floating gate with array of nanocrystals. Germanium (Ge) is a good candidate for nanocrystal based flash memories due its small band gap. In this work, we present effect of silicon dioxide (SiO 2) host matrix density on Ge nanocrystals morphology. Low density Ge+SiO 2 layers are deposited between high density SiO 2 layers by using off-angle magnetron sputter deposition. After high temperature post-annealing, faceted and elongated Ge nanocrystals formation is observed in low density layers. Effects of Ge concentration and annealing temperature on nanocrystal morphology and mean size were investigated by using transmission electron microscopy. Positive correlation between stress development and nanocrystal size is observed at Raman spectroscopy measurements. We concluded that non-uniform stress distribution on nanocrystals during growth is responsible from faceted and elongated nanocrystal morphology.Item Open Access Memory effect by charging of ultra‐small 2‐nm laser‐synthesized solution processable Si‐nanoparticles embedded in Si–Al2O3–SiO2 structure(Wiley-VCH Verlag, 2015) El-Atab, N.; Rizk, A.; Tekcan, B.; Alkis, S.; Okyay, Ali Kemal; Nayfeh, A.A memory structure containing ultra-small 2-nm laser-synthesized silicon nanoparticles is demonstrated. The Si-nanoparticles are embedded between an atomic layer deposited high-κ dielectric Al2O3 layer and a sputtered SiO2 layer. A memory effect due to charging of the Si nanoparticles is observed using high frequency C-V measurements. The shift of the threshold voltage obtained from the hysteresis measurements is around 3.3V at 10/-10V gate voltage sweeping. The analysis of the energy band diagram of the memory structure and the negative shift of the programmed C-V curve indicate that holes are tunneling from p-type Si via Fowler-Nordheim tunneling and are being trapped in the Si nanoparticles. In addition, the structures show good endurance characteristic (>105program/erase cycles) and long retention time (>10 years), which make them promising for applications in non-volatile memory devices. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.Item Open Access Memristive behavior in a junctionless flash memory cell(American Institute of Physics Inc., 2015) Orak, I.; Ürel, M.; Bakan, G.; Dana, A.We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO2 as the tunnel dielectric, AI2O3 as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits the pinched hysteresis of a memristor and in the unoptimized device, R off/R on ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts Roff/Ron ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 106 s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.Item Open Access Technical note-optimal structural results for assemble-to-order generalized M-Systems(INFORMS Inst.for Operations Res.and the Management Sciences, 2014) Nadar, E.; Akan, M.; Scheller-Wolf, A.We consider an assemble-to-order generalized M-system with multiple components and multiple products, batch ordering of components, random lead times, and lost sales. We model the system as an infinite-horizon Markov decision process and seek an optimal policy that specifies when a batch of components should be produced (i.e., inventory replenishment) and whether an arriving demand for each product should be satisfied (i.e., inventory allocation). We characterize optimal inventory replenishment and allocation policies under a mild condition on component batch sizes via a new type of policy: lattice-dependent base stock and lattice-dependent rationing. © 2014 INFORMS.Item Open Access Thin-film ZnO charge-trapping memory cell grown in a single ALD step(Institute of Electrical and Electronics Engineers, 2012-10-26) Oruc, F. B.; Cimen, F.; Rizk, A.; Ghaffari, M.; Nayfeh, A.; Okyay, Ali KemalA thin-film ZnO-based single-transistor memory cell with a gate stack deposited in a single atomic layer deposition step is demonstrated. Thin-film ZnO is used as channel material and charge-trapping layer for the first time. The extracted mobility and subthreshold slope of the thin-film device are 23 cm2/V · s and 720 mV/dec, respectively. The memory effect is verified by a 2.35-V hysteresis in the $I\rm drain- $V\rm gate curve. Physics-based TCAD simulations show very good agreement with the experimental results providing insight to the charge-trapping physics.Item Open Access Two-nanometer laser synthesized Si-nanoparticles for low power memory applications(Springer International Publishing, 2016) El-Atab, N.; Okyay, Ali Kemal; Nayfeh, A.Current flash memory devices are expected to face two major challenges in the near future: density and voltage scaling. The density of the memory is related to the gate length scaling which is constrained by the gate stack, namely, the tunnel oxide thickness. In fact, the gate length is required to be commensurate with the gate stack in order to maintain a good gate control and to avoid short channel effects. However, in conventional flash memories, the tunnel oxide thickness has a lower limit of 6-7 nm (depending on NOR or NAND structure) in order to avoid back-tunneling and thus leakage of charges which destroys the necessary retention characteristic of the memory (>10 years). The second problem which needs to be solved is the high program and erase operating voltages. Once again, the limitation to operating voltage scaling is the inability to reduce gate stack thickness. Therefore, it is imperative to find novel structures and materials to be incorporated in the memory cells which would allow tunnel oxide and voltage scaling. In this study, MOSFET- and MOSCAP-based memory devices are investigated along with the use of 2-nm silicon nanoparticles (Si-NPs) for charge storage. Atomic layer deposition is used to deposit the active layer of the memory and the spin coating is performed to deliver the Si-nanoparticles across the sample.