Browsing by Subject "Compiler"
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Item Open Access ABC: a double-conversion compiler/solver for nanoscience calculus(Computational Publications, 2003) Kulik, Igor O."CompLab" ("Compiler Laboratory") or "ABC" ("Advanced Basic-C") is a double conversion compiler working in two parallel regimes (A and B) one of which is similar to that of MATLAB while the other is a professional compilation routine similar to C and FORTRAN languages. Double-conversion scheme of compilation allows making advantage of both the simplicity of used code (program, commands) and at the same time of the power of C language in speed and in the capacity of CPU memory usage. The "A" regime allows for on-line calculation of multidimensional integrals, eigenvalues of large matrices, roots of nonlinear equations, plotting functions and their derivatives, etc. The "B" regime is an exportable program of conversion from the pseudobasic input code to C-code, compilation and solution. The C-code is fit for usage in any computational platform including Windows, OS/2, Linux and Unix machines.Item Open Access Çizge uygulamalarına özel işlemci tasarımı(IEEE, 2022-08-29) Pulat, Gülce; Saeed, Aamir; Yenimol, Mehmetali Semi; Gülgeç, Utku; Öztürk, ÖzcanBir çok büyük veri işleme uygulaması “PageRank”, “İşbirliğine Dayalı Filtreleme” ve “Betweenness Centrality” gibi düzensiz ve yinelemeli çizge algoritmalarından yararlanmaktadır. Çizge yapılarında her bir düğüm bir kişiye ya da nesneye karşılık gelirken, her bir ayrıt da bir kişi ya da nesne çifti arasındaki ilişkiye karşılık gelmektedir. Böylesi büyük verileri işleyen algoritmaları yürütecek genel amaçlı işlemciler yetersiz kalabilmektedir. Özellikle, güç kısıtları sebebiyle işlemci alt parçalarından sadece bir kısmı aynı anda aktif olarak kullanılabilmektedir. Bu da işlemcinin etkin olarak kullanılmasına engel olarak aktif olmayan “karanlık silikon”lar ortaya çıkarmaktadır. Bu bildirinin amacı da büyük verili ve düzensiz çizge uygulamalarını hızlı, verimli ve kolay programlanabilir biçimde çalıştıracak bir işlemci mimarisi tasarlamaktır. Literatürde çizge uygulamaları için daha önce sunulmuş çalışmalar çoğunlukla sadece yazılım ya da hızlandırıcı seviyesindedir. İşlemci seviyesi tasarımlar ise donanımsal maliyet, talep ettikleri mimari destek ve komut seti değişiklikleri açılarından bu bildiri kapsamında tanıtılacak işlemciden farklıdır.Item Open Access Compiler directed network-on-chip reliability enhancement for chip multiprocessors(Association for Computing Machinery, 2010-04) Ozturk, O.; Kandemir, M.; Irwin, M. J.; Narayanan, S.H. K.Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, programming them is even more challenging. As the number of cores accommodated in chip multiprocessors increases, network-on-chip (NoC) type communication fabrics are expected to replace traditional point-to-point buses. Most of the prior software related work so far targeting CMPs focus on performance and power aspects. However, as technology scales, components of a CMP are being increasingly exposed to both transient and permanent hardware failures. This paper presents and evaluates a compiler-directed power-performance aware reliability enhancement scheme for network-on-chip (NoC) based chip multiprocessors (CMPs). The proposed scheme improves on-chip communication reliability by duplicating messages traveling across CMP nodes such that, for each original message, its duplicate uses a different set of communication links as much as possible (to satisfy performance constraint). In addition, our approach tries to reuse communication links across the different phases of the program to maximize link shutdown opportunities for the NoC (to satisfy power constraint). Our results show that the proposed approach is very effective in improving on-chip network reliability, without causing excessive power or performance degradation. In our experiments, we also evaluate the performance oriented and energy oriented versions of our compiler-directed reliability enhancement scheme, and compare it to two pure hardware based fault tolerant routing schemes. © 2010 ACM.Item Open Access Compiler-supported selective software fault tolerance(IEEE, 2023-11-15) Turhan, Tuncer; Tekgul, H.; Öztürk, ÖzcanAs technology advances, the processors are shrunk in size and manufactured using higher-density transistors, making them cheaper, more power efficient, and more powerful. While this progress is most beneficial to end-users, these advances make processors more vulnerable to outside radiation, causing soft errors, mostly in single-bit flips on data. In applications where a certain margin of error is acceptable, and availability is important, the existing software fault tolerance techniques may not be applied directly because of the unacceptable performance overheads they introduce to the system. We propose a technique that ranks the instructions in terms of their criticality and generates a more reliable source code. This way, we improve reliability and minimize the performance overheads.Item Open Access A decoupled local memory allocator(Association for Computing Machinery, 2013) Diouf, B.; Hantaş, C.; Cohen, A.; Özturk, Ö.; Palsberg, J.Compilers use software-controlled local memories to provide fast, predictable, and power-efficient access to critical data. We show that the local memory allocation for straight-line, or linearized programs is equivalent to a weighted interval-graph coloring problem. This problem is new when allowing a color interval to "wrap around," and we call it the submarine-building problem. This graph-theoretical decision problem differs slightly from the classical ship-building problem, and exhibits very interesting and unusual complexity properties. We demonstrate that the submarine-building problem is NP-complete, while it is solvable in linear time for not-so-proper interval graphs, an extension of the the class of proper interval graphs. We propose a clustering heuristic to approximate any interval graph into a not-so-proper interval graph, decoupling spill code generation from local memory assignment. We apply this heuristic to a large number of randomly generated interval graphs reproducing the statistical features of standard local memory allocation benchmarks, comparing with state-of-the-art heuristics. © 2013 ACM.Item Restricted Geleneksel Türk masalına çağdaş yaklaşımıyla Oğuz Tansel(Bilkent University, 2024) Koç, Bahar; Şekerci, Dicle; Doğan, Senay Bilge; Erensoy, Demir; Emir, EgeBu çalışma; Türk Edebiyatının önemli isimlerinden olan şair, yazar, masal derlemecisi ve halk bilimci Oğuz Tansel’i incelemektedir. Çalışmanın amacı; Oğuz Tansel’i, eserlerini, katkılarını, dünya görüşünü daha iyi anlamak ve anlatmaktır. Türk Dil Kurumu tarafından verilen Çocuk Yazın Ödülü’nün ilk sahibi Tansel’in hayatı, etkilendiği akımlar ve yazarlar, benimsediği toplumsal ve siyasi görüşler bağlamında eserleri ele alınacaktır. Ardından Türk Edebiyatına olan katkısı ve mirasının üzerinde durulacaktır.Item Open Access Profiler and compiler assisted adaptive I/O prefetching for shared storage caches(ACM, 2008-10) Son, S. W.; Kandemir, M.; Kolcu, I.; Muralidhara, S. P.; Öztürk, Öztürk; Karakoy, M.I/O prefetching has been employed in the past as one of the mech- anisms to hide large disk latencies. However, I/O prefetching in parallel applications is problematic when multiple CPUs share the same set of disks due to the possibility that prefetches from different CPUs can interact on shared memory caches in the I/O nodes in complex and unpredictable ways. In this paper, we (i) quantify the impact of compiler-directed I/O prefetching - developed originally in the context of sequential execution - on shared caches at I/O nodes. The experimental data collected shows that while I/O prefetching brings benefits, its effectiveness reduces significantly as the number of CPUs is increased; (ii) identify inter-CPU misses due to harmful prefetches as one of the main sources for this re- duction in performance with the increased number of CPUs; and (iii) propose and experimentally evaluate a profiler and compiler assisted adaptive I/O prefetching scheme targeting shared storage caches. The proposed scheme obtains inter-thread data sharing information using profiling and, based on the captured data sharing patterns, divides the threads into clusters and assigns a separate (customized) I/O prefetcher thread for each cluster. In our approach, the compiler generates the I/O prefetching threads automatically. We implemented this new I/O prefetching scheme using a compiler and the PVFS file system running on Linux, and the empirical data collected clearly underline the importance of adapting I/O prefetching based on program phases. Specifically, our pro- posed scheme improves performance, on average, by 19.9%, 11.9% and http://dx.doi.org/10.3% over the cases without I/O prefetching, with independent I/O prefetching (each CPU is performing compiler-directed I/O prefetching independently), and with one CPU prefetching (one CPU is reserved for prefetching on behalf of others), respectively, when 8 CPUs are used. Copyright 2008 ACM.Item Open Access Reducing memory space consumption through dataflow analysis(Pergamon Press, 2011) Ozturk, O.Memory is a key parameter in embedded systems since both code complexity of embedded applications and amount of data they process are increasing. While it is true that the memory capacity of embedded systems is continuously increasing, the increases in the application complexity and dataset sizes are far greater. As a consequence, the memory space demand of code and data should be kept minimum. To reduce the memory space consumption of embedded systems, this paper proposes a control flow graph (CFG) based technique. Specifically, it tracks the lifetime of instructions at the basic block level. Based on the CFG analysis, if a basic block is known to be not accessible in the rest of the program execution, the instruction memory space allocated to this basic block is reclaimed. On the other hand, if the memory allocated to this basic block cannot be reclaimed, we try to compress this basic block. This way, it is possible to effectively use the available on-chip memory, thereby satisfying most of instruction/data requests from the on-chip memory. Our experiments with this framework show that it outperforms the previously proposed CFG-based memory reduction approaches. © 2011 Elsevier Ltd. All rights reserved.