Browsing by Subject "Charge trapping memory"

Now showing 1 - 8 of 8

Open Access
2-nm laser-synthesized Si nanoparticles for low-power charge trapping memory devices
(IEEE, 2014-08) El-Atab, N.; Özcan, Ayşe; Alkış, Sabri; Okyay, Ali Kemal; Nayfeh, A.
In this work, the effect of embedding Silicon Nanoparticles (Si-NPs) in ZnO based charge trapping memory devices is studied. Si-NPs are fabricated by laser ablation of a silicon wafer in deionized water followed by sonication and filtration. The active layer of the memory was deposited by Atomic Layer Deposition (ALD) and spin coating technique was used to deliver the Si-NPs across the sample. The nanoparticles provided a good retention of charges (>10 years) in the memory cells and allowed for a large threshold voltage (Vt) shift (3.4 V) at reduced programming voltages (1 V). The addition of ZnO to the charge trapping media enhanced the electric field across the tunnel oxide and allowed for larger memory window at lower operating voltages. © 2014 IEEE.
Open Access
Charge Trapping Memory with 2.85-nm Si-Nanoparticles Embedded in HfO2
(ECS, 2015-05) El-Atab, N.; Turgut, Berk Berkan; Okyay, Ali Kemal; Nayfeh, A.
In this work, the effect of embedding 2.85-nm Si-nanoparticles charge trapping layer in between double layers of high-κ Al2O3/HfO2 oxides is studied. Using high frequency (1 MHz) C-Vgate measurements, the memory showed a large memory window at low program/erase voltages due to the charging of the Si-nanoparticles. The analysis of the C-V characteristics shows that mixed charges are being stored in the Si-nanoparticles where electrons get stored during the program operation while holes dominate in the Si-nanoparticles during the erase operation. Moreover, the retention characteristic of the memory is studied by measuring the memory hysteresis in time. The obtained retention characteristic (35.5% charge loss in 10 years) is due to the large conduction and valence band offsets between the Si-nanoparticles and the Al2O3/HfO2 tunnel oxide. The results show that band engineering is essential in future low-power non-volatile memory devices. In addition, the results show that Si-nanoparticles are promising in memory applications.
Open Access
Enhanced non-volatile memory characteristics with quattro-layer graphene nanoplatelets vs. 2.85-nm Si nanoparticles with asymmetric Al2O3/HfO2 tunnel oxide
(Springer New York LLC, 2015) El-Atab, N.; Turgut, B. B.; Okyay, Ali Kemal; Nayfeh, M.; Nayfeh, A.
In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al2O3/HfO2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al2O3/HfO2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics.
Open Access
Low power Zinc-Oxide based charge trapping memory with embedded silicon nanoparticles
(ECS, 2014) Nayfeh, A.; Okyay, Ali Kemal; El-Atab, N.; Özcan, Ayşe; Alkış, Sabri
In this work, a bottom-gate charge trapping memory device with Zinc-Oxide (ZnO) channel and 2-nm Si nanoparticles (Si-NPs) embedded in ZnO charge trapping layer is demonstrated. The active layers of the memory device are deposited by atomic layer deposition (ALD) and the Si-NPs are deposited by spin coating. The Si-NPs memory exhibits a threshold voltage (Vt) shift of 6.3 V at an operating voltage of -10/10 V while 2.6 V Vt shift is obtained without nanoparticles confirming that the Si-NPs act as energy states within the bandgap of the ZnO layer. In addition, a 3.4 V Vt is achieved at a very low operating voltage of -1 V/1 V due to the charging of the Si-NPs through Poole-Frenkel emission mechanism at an electric field across the tunnel oxide E > 0.36 MV/cm. The results highlight a promising technology for future ultra-low power memory devices.
Open Access
Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission
(2014) El-Atab, N.; Ozcan, A.; Alkis, S.; Okyay, Ali Kemal; Nayfeh, A.
A low power zinc-oxide (ZnO) charge trapping memory with embedded silicon (Si) nanoparticles is demonstrated. The charge trapping layer is formed by spin coating 2 nm silicon nanoparticles between Atomic Layer Deposited ZnO steps. The threshold voltage shift (ΔVt) vs. programming voltage is studied with and without the silicon nanoparticles. Applying -1 V for 5 s at the gate of the memory with nanoparticles results in a ΔVt of 3.4 V, and the memory window can be up to 8 V with an excellent retention characteristic (>10 yr). Without nanoparticles, at -1 V programming voltage, the ΔVt is negligible. In order to get ΔVt of 3.4 V without nanoparticles, programming voltage in excess of 10 V is required. The negative voltage on the gate programs the memory indicating that holes are being trapped in the charge trapping layer. In addition, at 1 V the electric field across the 3.6 nm tunnel oxide is calculated to be 0.36 MV/cm, which is too small for significant tunneling. Moreover, the ΔVt vs. electric field across the tunnel oxide shows square root dependence at low fields (E 1 MV/cm) and a square dependence at higher fields (E > 2.7 MV/cm). This indicates that Poole-Frenkel Effect is the main mechanism for holes emission at low fields and Phonon Assisted Tunneling at higher fields. © 2014 AIP Publishing LLC.
Open Access
Memory effect by charging of ultra‐small 2‐nm laser‐synthesized solution processable Si‐nanoparticles embedded in Si–Al2O3–SiO2 structure
(Wiley-VCH Verlag, 2015) El-Atab, N.; Rizk, A.; Tekcan, B.; Alkis, S.; Okyay, Ali Kemal; Nayfeh, A.
A memory structure containing ultra-small 2-nm laser-synthesized silicon nanoparticles is demonstrated. The Si-nanoparticles are embedded between an atomic layer deposited high-κ dielectric Al2O3 layer and a sputtered SiO2 layer. A memory effect due to charging of the Si nanoparticles is observed using high frequency C-V measurements. The shift of the threshold voltage obtained from the hysteresis measurements is around 3.3V at 10/-10V gate voltage sweeping. The analysis of the energy band diagram of the memory structure and the negative shift of the programmed C-V curve indicate that holes are tunneling from p-type Si via Fowler-Nordheim tunneling and are being trapped in the Si nanoparticles. In addition, the structures show good endurance characteristic (>105program/erase cycles) and long retention time (>10 years), which make them promising for applications in non-volatile memory devices. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Open Access
Novel materials for thin-film memory cells
(2014) Çimen, Furkan
The tremendous growth in consumer electronics market increased the need for low-cost, low-power and high quality memory chips. This challenge is further aggravated by the continuous increase in density and scaling of the gate length, since it creates a major challenge for current nonvolatile flash memory devices to maintain reliability and retention. Therefore, it is imperative to find new materials and novel fabrication processes to be incorporated in memory cells in order to keep up with the enormous rate of increase in consumer needs. In the first part of this thesis, we demonstrate a charge trapping memory with graphene nanoplatelets embedded in atomic layer deposited ZnO. We first introduce the fabrication process for the memory device and then investigate the memory characteristics. Our experimental analysis on the memory cell shows a large threshold voltage Vt shift (4V ) at low operating voltages (6/ − 6V ), good retention (> 10 years), and good endurance characteristics (> 104 cycles). The resulting memory behavior is also verified by theoretical computations. In the second part, we demonstrate the use of laser-synthesized indium-nitride nanoparticles (InN-NPs) as the charge trapping layer in the memory cell. We first introduce the indium-nitride nanoparticle synthesis and then detail the fabrication process of the memory device. The experimental analysis of the memory cell results in a noticeable threshold voltage Vt shift (2V ) at low operating voltages (4V ) in addition to the similar retention and endurance performance with the graphene-based memory cells. The memory behavior was also verified with theoretical computations for the InN-NPs based memory cells. In the last part of this thesis, we demonstrate a memory device with a gate stack fabricated in a single ALD step. Single-step all-ALD approach avoids the risk of contamination and incorporation of impurities in the gate stack. It also allows low-cost production by eliminating multiple equipment utilization. Motivated by these, we first present the fabrication process of the memory device and then explain the experimental and theoretical characterization and analysis. The memory effect of the thin-film ZnO charge-trapping memory cell is verified by a 2.35V hysteresis in drain current vs. gate voltage curve. The resulting memory behavior is also verified by physics-based TCAD simulations.
Open Access
Silicon nanoparticle charge trapping memory cell
(Wiley-VCH Verlag, 2014) El-Atab, N.; Ozcan, A.; Alkis, S.; Okyay, Ali Kemal; Nayfeh, A.
A charge trapping memory with 2 nm silicon nanoparticles (Si NPs) is demonstrated. A zinc oxide (ZnO) active layer is deposited by atomic layer deposition (ALD), preceded by Al2O3 which acts as the gate, blocking and tunneling oxide. Spin coating technique is used to deposit Si NPs across the sample between Al2O3 steps. The Si nanoparticle memory exhibits a threshold voltage (Vt) shift of 2.9 V at a negative programming voltage of -10 V indicating that holes are emitted from channel to charge trapping layer. The negligible measured Vt shift without the nanoparticles and the good re- tention of charges (>10 years) with Si NPs confirm that the Si NPs act as deep energy states within the bandgap of the Al2O3 layer. In order to determine the mechanism for hole emission, we study the effect of the electric field across the tunnel oxide on the magnitude and trend of the Vt shift. The Vt shift is only achieved at electric fields above 1 MV/cm. This high field indicates that tunneling is the main mechanism. More specifically, phonon-assisted tunneling (PAT) dominates at electric fields between 1.2 MV/cm < E < 2.1 MV/cm, while Fowler-Nordheim tunneling leads at higher fields (E > 2.1 MV/cm). © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.