Browsing by Subject "3D"

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    Design and finite element simulation of a novel 3D-CMUT device for simultaneous sensing of in-plane and out-of-plane displacements of ultrasonic guided waves
    (MDPI AG, 2023-10-25) Zhang, S.; Lu, W.; Wang, A.; Hao, G.; Wang, R.; Yilmaz, Mehmet
    In this study, we introduce a physical model of a three-dimensional (3D) guided wave sensor called 3D-CMUT, which is based on capacitive micro-machined ultrasonic transducers (CMUTs). This 3D-CMUT sensor is designed to effectively and simultaneously obtain 3D vibration information about ultrasonic guided waves in the out-of-plane (z-direction) and in-plane (x and y-directions). The basic unit of the 3D-CMUT is much smaller than the wavelength of the guided waves and consists of two orthogonal comb-like CMUT cells and one piston-type CMUT cell. These cells are used to sense displacement signals in the x, y, and z-directions. To ensure proper functioning of the 3D-CMUT unit, the resonant frequencies of the three composed cells are set to be identical by adjusting the microstructural parameters appropriately. Moreover, the same sensitivity in the x, y, and z-directions is theoretically achieved by tuning the amplification parameters in the external circuit. We establish a transient analysis model of the 3D-CMUT using COMSOL finite element simulation software to confirm its ability to sense multimode ultrasonic guided waves, including A0, S0, and SH0 modes. Additionally, we simulate the ball drop impact acoustic emission signal on a plate to demonstrate that the 3D-CMUT can not only utilize in-plane information for positioning but also out-of-plane information. The proposed 3D-CMUT holds significant potential for applications in the field of structural health monitoring (SHM).
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    Energy reduction in 3D NoCs through communication optimization
    (Springer Wien, 2015) Ozturk, O.; Akturk I.; Kadayif I.; Tosun, S.
    Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. Specifically, on a heterogeneous 3D NoC architecture, we explore how different types of processors can be optimally placed to minimize data access costs. Moreover, we select the optimal set of links with optimal voltage levels. The experimental results indicate significant savings in energy consumption across a wide range of values of our major simulation parameters.
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    ILP-based communication reduction for heterogeneous 3D network-on-chips
    (IEEE, 2013-02-03) Aktürk, İsmail; Öztürk, Özcan
    Network-on-Chip (NoC) architectures and three-dimensional integrated circuits (3D ICs) have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. We explore how heterogeneous processors can be mapped onto the given 3D chip area to minimize the data access costs. Our initial results indicate that the proposed approach generates promising results within tolerable solution times. © 2013 IEEE.
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    Reliability-aware 3D chip multiprocessor design
    (IEEE, 2012-06) Öztürk, Özcan; Aktürk, İsmail
    Ability to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit area. An important issue in designing a heterogeneous 3D IC is reliability. To achieve this, one needs to select the data mapping and processor layout carefully. In this paper, we try to perform this mapping and processor layout effectively. Specifically, on a heterogeneous 3D CMP, we explore how applications can be mapped onto 3D ICs to maximize reliability. Our preliminary experimental evaluation indicates that the proposed technique generates promising results in both reliability and performance.
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    ItemOpen Access
    Reliability-aware heterogeneous 3D chip multiprocessor design
    (Springer, 2013) Akturk, I.; Ozturk, O.
    Ability to stack separate chips in a single package enables three-dimensional integrated circuits (3D ICs). Heterogeneous 3D ICs provide even better opportunities to reduce the power and increase the performance per unit area. An important issue in designing a heterogeneous 3D IC is reliability. To achieve this, one needs to select the data mapping and processor layout carefully. This paper addresses this problem using an integer linear programming (ILP) approach. Specifically, on a heterogeneous 3D CMP, it explores how applications can be mapped onto 3D ICs to maximize reliability. Preliminary experiments indicate that the proposed technique generates promising results in both reliability and performance. © 2013 Springer Science+Business Media New York.