Application-specific heterogeneous network-on-chip design

buir.advisorÖztürk, Özcan
dc.contributor.authorDemirbaş, Dilek
dc.date.accessioned2016-01-08T18:15:22Z
dc.date.available2016-01-08T18:15:22Z
dc.date.issued2011
dc.descriptionAnkara : The Department of Computer Engineering and the Institute of Engineering and Science of Bilkent University, 2011.en_US
dc.descriptionThesis (Master's) -- Bilkent University, 2011.en_US
dc.descriptionIncludes bibliographical references leaves 68-74.en_US
dc.description.abstractWith increasing communication demands of processors and memory cores in Systems-on-Chips (SoCs), application-specific and scalable Network-on-Chips (NoCs) are emerged to interconnect processing cores and subsystems in Multiprocessor System-on-Chips (MPSoCs). The challenge of application-specific NoC design is to find the right balance among different trade-offs such as communication latency, power consumption, and chip area. This thesis introduces a novel heterogeneous NoC design approach where biologically inspired evolutionary algorithm and 2-dimensional rectangle packing algorithm are used to place the processing elements with various properties into a constrained NoC area according to the tasks generated by Task Graph for Free (TGFF). TGFF is one of the pseudo-random task graph generators used for scheduling and allocation. Based on a given task graph, we minimize the maximum execution time in a Heterogeneous Chip-Multiprocessor. We specifi- cally emphasize on the communication cost as it is a big overhead in a multi-core architecture. Experimental results show that our approach improves total communication latency up to 27% with modest power consumption.en_US
dc.description.provenanceMade available in DSpace on 2016-01-08T18:15:22Z (GMT). No. of bitstreams: 1 0005080.pdf: 3181348 bytes, checksum: ce7b5dde5c6e7669f22c93e2ad82a087 (MD5)en
dc.description.statementofresponsibilityDemirbaş, Dileken_US
dc.format.extentxi, 90 leaves, illustrationsen_US
dc.identifier.urihttp://hdl.handle.net/11693/15235
dc.language.isoEnglishen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectNetwork-on-Chip (NoC) synthesisen_US
dc.subjectMultiprocessor-System-on-Chip (MPSoC) designen_US
dc.subjectHeterogeneous Chip-Multiprocessorsen_US
dc.subject.lccTK5105.546 .D45 2011en_US
dc.subject.lcshNetworks on a chip.en_US
dc.subject.lcshMicroprocessor system on chip.en_US
dc.subject.lcshSystems on a chip.en_US
dc.subject.lcshComputer networks.en_US
dc.titleApplication-specific heterogeneous network-on-chip designen_US
dc.typeThesisen_US
thesis.degree.disciplineComputer Engineering
thesis.degree.grantorBilkent University
thesis.degree.levelMaster's
thesis.degree.nameMS (Master of Science)

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