Memristive behavior in a junctionless flash memory cell
dc.citation.epage | 233506-5 | en_US |
dc.citation.issueNumber | 23 | en_US |
dc.citation.spage | 233506 | en_US |
dc.citation.volumeNumber | 106 | en_US |
dc.contributor.author | Orak, I. | en_US |
dc.contributor.author | Ürel, M. | en_US |
dc.contributor.author | Bakan, G. | en_US |
dc.contributor.author | Dana, A. | en_US |
dc.date.accessioned | 2016-02-08T09:50:38Z | |
dc.date.available | 2016-02-08T09:50:38Z | |
dc.date.issued | 2015 | en_US |
dc.department | Institute of Materials Science and Nanotechnology (UNAM) | en_US |
dc.description.abstract | We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO2 as the tunnel dielectric, AI2O3 as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits the pinched hysteresis of a memristor and in the unoptimized device, R off/R on ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts Roff/Ron ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 106 s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable. | en_US |
dc.description.provenance | Made available in DSpace on 2016-02-08T09:50:38Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 70227 bytes, checksum: 26e812c6f5156f83f0e77b261a471b5a (MD5) Previous issue date: 2015 | en_US |
dc.identifier.doi | 10.1063/1.4922624 | en_US |
dc.identifier.issn | 0003-6951 | |
dc.identifier.uri | http://hdl.handle.net/11693/21747 | |
dc.language.iso | English | en_US |
dc.publisher | American Institute of Physics Inc. | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1063/1.4922624 | en_US |
dc.source.title | Applied Physics Letters | en_US |
dc.subject | Atomic layer deposition | en_US |
dc.subject | Electric grounding | en_US |
dc.subject | Memory architecture | en_US |
dc.subject | Memristors | en_US |
dc.subject | Monolithic microwave integrated circuits | en_US |
dc.subject | Passive filters | en_US |
dc.subject | Semiconductor storage | en_US |
dc.subject | Silicon nitride | en_US |
dc.subject | Threshold voltage | en_US |
dc.subject | Control dielectrics | en_US |
dc.subject | Low operating voltage | en_US |
dc.subject | Memristive behavior | en_US |
dc.subject | Neuromorphic computing | en_US |
dc.subject | Processing applications | en_US |
dc.subject | Resistive switching | en_US |
dc.subject | Tunnel dielectrics | en_US |
dc.subject | Two-terminal devices | en_US |
dc.subject | Flash memory | en_US |
dc.title | Memristive behavior in a junctionless flash memory cell | en_US |
dc.type | Article | en_US |
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