VLSI circuit partitioning for simulation and placement

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buir.supervisorAykanat, Cevdet
dc.contributor.authorTahboub, Radwan
dc.date.accessioned2016-01-08T20:10:50Z
dc.date.available2016-01-08T20:10:50Z
dc.date.copyright1993-01
dc.date.issued1993-01
dc.description Cataloged from PDF version of article.en_US
dc.descriptionThesis (Master's): Department of Computer Engineering and Information Science and Institute of Engineering and Science, Bilkent Univ., 1993.en_US
dc.descriptionIncludes bibliographical references (leaves 71-76).en_US
dc.description.abstractSimulation time of Very Large Scale Integrated (VLSI) circuits may be improved substantially upon the partitioning of the circuit into several smaller sub-circuits. Node Splitting (NS) is the underlying basis for partitioning of large integrated circuits into several, more manageable, and sometimes similar sub-circuits to enhance computer simulation efficiency. In this thesis, a partitioning scheme based on the NS is used to partition VLSI circuits efficiently. The proposed algorithms will be used as a preprocessing step to increase the efficiency of a VLSI analog circuit simulator designed by the EE Department at Bilkent University. With small modifications, the same algorithms are used to form clusters of transistors based on their interconnections. The clustered circuit will then be partitioned using well known heuristics such as Simulated Annealing and Kernighan-Lin to be used in VLSI placement. The results with this method have been superior to those with the conventional implementations. We have observed a factor of 3-4 speed-up in CPU time, together with 5-10% improvement in the cut size. Experimental results show that the proposed algorithms can be efficiently used in VLSI circuit partitioning for simulation and placement.
dc.description.provenanceMade available in DSpace on 2016-01-08T20:10:50Z (GMT). No. of bitstreams: 1 1.pdf: 78510 bytes, checksum: d85492f20c2362aa2bcf4aad49380397 (MD5)en
dc.description.statementofresponsibility Radwan Tahboub en_US
dc.format.extentxii, 76 leaves, illustrations ; 30 cmen_US
dc.identifier.itemidBILKUTUPB001426
dc.identifier.urihttp://hdl.handle.net/11693/17498
dc.language.isoEnglishen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectVLSI circuit simulation
dc.subjectPlacement
dc.subjectNode splitting
dc.subjectPartitioning
dc.subjectSimulated annealing
dc.subjectKernighan-Lin
dc.titleVLSI circuit partitioning for simulation and placementen_US
dc.title.alternativeBenzetim ve yerleştirme için çok geniş ölçekli (VLSI) devre parçalama
dc.typeThesisen_US
thesis.degree.disciplineComputer Engineering
thesis.degree.grantorBilkent University
thesis.degree.levelMaster's
thesis.degree.nameMS (Master of Science)

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