VLSI circuit partitioning for simulation and placement
Simulation time of Very Large Scale Integrated (VLSI) circuits may be improved substantially upon the partitioning of the circuit into several smaller sub-circuits. Node Splitting (NS) is the underlying basis for partitioning of large integrated circuits into several, more manageable, and sometimes similar sub-circuits to enhance computer simulation efficiency. In this thesis, a partitioning scheme based on the NS is used to partition VLSI circuits efficiently. The proposed algorithms will be used as a preprocessing step to increase the efficiency of a VLSI analog circuit simulator designed by the EE Department at Bilkent University. With small modifications, the same algorithms are used to form clusters of transistors based on their interconnections. The clustered circuit will then be partitioned using well known heuristics such as Simulated Annealing and Kernighan-Lin to be used in VLSI placement. The results with this method have been superior to those with the conventional implementations. We have observed a factor of 3-4 speed-up in CPU time, together with 5-10% improvement in the cut size. Experimental results show that the proposed algorithms can be efficiently used in VLSI circuit partitioning for simulation and placement.