FPGA implementation of a fault-tolerant application-specific NoC design

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dc.citation.epage6en_US
dc.citation.spage1en_US
dc.contributor.authorYeşil, Şerifen_US
dc.contributor.authorTosun, S.en_US
dc.contributor.authorÖztürk, Özcanen_US
dc.coverage.spatialIstanbul, Turkey
dc.date.accessioned2018-04-12T11:50:07Z
dc.date.available2018-04-12T11:50:07Z
dc.date.issued2016-04en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 12-14 April 2016
dc.descriptionConference name: 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)
dc.description.abstractToday's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem is fatal to application-specific Network-on-Chip (NoC) designs as well if they cannot tolerate such failures. One solution to this problem can be having alternative routing options on the network for each communicating pair. In this study, we present an FPGA implementation of such a method for application-specific NoCs. This method adds additional network resources to the non-fault-tolerant design in an attempt to make it fault-tolerant. We show the effects of the presented fault-tolerant method on an FPGA implementation of Mp3 encoder based on energy consumption and area increase against non-fault-tolerant case. © 2016 IEEE.en_US
dc.description.provenanceMade available in DSpace on 2018-04-12T11:50:07Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 179475 bytes, checksum: ea0bedeb05ac9ccfb983c327e155f0c2 (MD5) Previous issue date: 2016en
dc.identifier.doi10.1109/DTIS.2016.7483876en_US
dc.identifier.urihttp://hdl.handle.net/11693/37752
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/DTIS.2016.7483876en_US
dc.source.title2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)en_US
dc.subjectDesignen_US
dc.subjectEnergy utilizationen_US
dc.subjectFault toleranceen_US
dc.subjectField programmable gate arrays (FPGA)en_US
dc.subjectIntegrated controlen_US
dc.subjectNanotechnologyen_US
dc.subjectNetwork-on-chipen_US
dc.subjectReconfigurable hardwareen_US
dc.subjectRoutersen_US
dc.subjectTelecommunication linksen_US
dc.subjectApplication specificen_US
dc.subjectApplication specific network on chipen_US
dc.subjectFault tolerant designen_US
dc.subjectFault-tolerant applicationsen_US
dc.subjectFault-tolerant methoden_US
dc.subjectFPGA implementationsen_US
dc.subjectNetwork resourceen_US
dc.subjectSingle-link failuresen_US
dc.subjectIntegrated circuit designen_US
dc.titleFPGA implementation of a fault-tolerant application-specific NoC designen_US
dc.typeConference Paperen_US

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