Hardware implementation of Fano Decoder for polarization-adjusted convolutional (PAC) codes

Abstract

Polarization-adjusted convolutional (PAC) codes are a new class of error-correcting codes that have been shown to achieve near-optimum performance. By combining ideas from channel polarization and convolutional coding, PAC codes create an overall encoding transform that achieves a performance near the information-theoretic limits at short block lengths. In this thesis we propose a hardware implementation architecture for Fano decoding of PAC codes. First, we introduce a new variant of Fano algorithm for decoding PAC codes which is suitable for hardware implementation. Then we provide the hardware diagrams of the sub-blocks of the proposed PAC Fano decoder and an estimate of their hardware complexity and propagation delay. We also introduce a novel branch metric unit for sequential decoding of PAC codes which is capable of calculating the current and previous branch metric values online, without requiring any storage element or comparator. We evaluate the error-correction performance of the proposed decoder on FPGA and its hardware characteristics on ASIC with TSMC 28 nm 0.72 V library. We show that, for a block length of 128 and a message length of 64, the proposed decoder can be clocked at 500 MHz and achieve approximately 38.1 Mb/s information throughput at 3.5 dB signal-to-noise ratio with a power consumption of 3.85 mW.