OptMem: dark-silicon aware low latency hybrid memory design

dc.contributor.authorOnsori, Salmanen_US
dc.contributor.authorAsad, Arghavan Aen_US
dc.contributor.authorRaahemifar, K.en_US
dc.contributor.authorFathy, M.en_US
dc.coverage.spatialBangalore, India
dc.date.accessioned2018-04-12T11:48:00Z
dc.date.available2018-04-12T11:48:00Z
dc.date.issued2016-01en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 10-12 Jan. 2016
dc.descriptionConference name: 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA)
dc.description.abstractIn this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static random access memory (SRAM) and spin-Transfer torque magnetic random-Access memory(STT-RAM) memories on the memory layer to exploit advantages of both technologies. Power consumption that is the main challenge in the dark silicon era is represented as a main constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D Chip-Multiprocessor (CMP). Experimental results show that the proposed architecture improves the energy consumption and performanceof the 3D CMPabout 25.8% and 12.9% on averagecompared to the Baseline memory design. © 2016 IEEE.en_US
dc.description.provenanceMade available in DSpace on 2018-04-12T11:48:00Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 179475 bytes, checksum: ea0bedeb05ac9ccfb983c327e155f0c2 (MD5) Previous issue date: 2016en
dc.identifier.doi10.1109/VLSI-SATA.2016.7593059en_US
dc.identifier.urihttp://hdl.handle.net/11693/37686en_US
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/VLSI-SATA.2016.7593059en_US
dc.source.title2016 International Conference on VLSI Systems, Architectures, Technology and Applications, VLSI-SATA 2016en_US
dc.subject3D integrationen_US
dc.subjectConvex optimizationen_US
dc.subjectDark siliconen_US
dc.subjectEmbedded chip-multiprocessor (eCMP)en_US
dc.subjectHybrid memory architectureen_US
dc.subjectNon-volatile memory (NVM)en_US
dc.subjectConvex optimizationen_US
dc.subjectData storage equipmenten_US
dc.subjectDigital storageen_US
dc.subjectEnergy utilizationen_US
dc.subjectIntegrated circuit designen_US
dc.subjectMagnetic storageen_US
dc.subjectMemory architectureen_US
dc.subjectMultiprocessing systemsen_US
dc.subjectOptimizationen_US
dc.subjectSiliconen_US
dc.subjectStatic random access storageen_US
dc.subjectVLSI circuitsen_US
dc.subject3-D integrationen_US
dc.subjectDark siliconsen_US
dc.subjectEmbedded chipsen_US
dc.subjectNon-volatile memoryen_US
dc.subjectUncore componentsen_US
dc.subjectRandom access storageen_US
dc.titleOptMem: dark-silicon aware low latency hybrid memory designen_US
dc.typeConference Paperen_US

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