A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model

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dc.citation.epage262en_US
dc.citation.spage261en_US
dc.contributor.authorOnsori, Salmanen_US
dc.contributor.authorAsad, Arghavanen_US
dc.contributor.authorRaahemifar, K.en_US
dc.contributor.authorFathy, M.en_US
dc.coverage.spatialGyungju, South Korea
dc.date.accessioned2018-04-12T11:49:00Z
dc.date.available2018-04-12T11:49:00Z
dc.date.issued2015-11en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 2-5 Nov. 2015
dc.descriptionConference name: 2015 International SoC Design Conference (ISOCC)
dc.description.abstractIn this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and maps applications/threads on cores in the core layer effectively. The detailed proposed model satisfies the power constraint which is the main challenge of dark-silicon era. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D eCMP compared to the Baseline memory design. © 2015 IEEE.en_US
dc.identifier.doi10.1109/ISOCC.2015.7401747en_US
dc.identifier.urihttp://hdl.handle.net/11693/37719
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/ISOCC.2015.7401747en_US
dc.source.titleISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)en_US
dc.subjectConvex-optimizationen_US
dc.subjectEmbedded chip-multiprocessor (eCMP)en_US
dc.subjectHybrid memory architectureen_US
dc.subjectNon-volatile memory (NVM)en_US
dc.subjectAdaptive systemsen_US
dc.subjectConvex optimizationen_US
dc.subjectData storage equipmenten_US
dc.subjectDesignen_US
dc.subjectDigital storageen_US
dc.subjectMultiprocessing systemsen_US
dc.subjectOptimizationen_US
dc.subjectProduct designen_US
dc.subjectProgrammable logic controllersen_US
dc.subjectRandom access storageen_US
dc.subjectStatic random access storageen_US
dc.subjectConvex modelingen_US
dc.subjectEmbedded chipsen_US
dc.subjectEnergy delay producten_US
dc.subjectMemory designen_US
dc.subjectMemory layersen_US
dc.subjectNon-volatile memoryen_US
dc.subjectPower constraintsen_US
dc.subjectProposed architecturesen_US
dc.subjectMemory architectureen_US
dc.titleA high-performance hybrid memory architecture for embedded CMPs using a convex optimization modelen_US
dc.typeConference Paperen_US

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