A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model
dc.citation.epage | 262 | en_US |
dc.citation.spage | 261 | en_US |
dc.contributor.author | Onsori, Salman | en_US |
dc.contributor.author | Asad, Arghavan | en_US |
dc.contributor.author | Raahemifar, K. | en_US |
dc.contributor.author | Fathy, M. | en_US |
dc.coverage.spatial | Gyungju, South Korea | |
dc.date.accessioned | 2018-04-12T11:49:00Z | |
dc.date.available | 2018-04-12T11:49:00Z | |
dc.date.issued | 2015-11 | en_US |
dc.department | Department of Computer Engineering | en_US |
dc.description | Date of Conference: 2-5 Nov. 2015 | |
dc.description | Conference name: 2015 International SoC Design Conference (ISOCC) | |
dc.description.abstract | In this article, we present a convex optimization model to design a stacked hybrid memory system for 3D embedded chip-multiprocessors (eCMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and maps applications/threads on cores in the core layer effectively. The detailed proposed model satisfies the power constraint which is the main challenge of dark-silicon era. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D eCMP compared to the Baseline memory design. © 2015 IEEE. | en_US |
dc.description.provenance | Made available in DSpace on 2018-04-12T11:49:00Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 179475 bytes, checksum: ea0bedeb05ac9ccfb983c327e155f0c2 (MD5) Previous issue date: 2016 | en |
dc.identifier.doi | 10.1109/ISOCC.2015.7401747 | en_US |
dc.identifier.uri | http://hdl.handle.net/11693/37719 | |
dc.language.iso | English | en_US |
dc.publisher | IEEE | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/ISOCC.2015.7401747 | en_US |
dc.source.title | ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE) | en_US |
dc.subject | Convex-optimization | en_US |
dc.subject | Embedded chip-multiprocessor (eCMP) | en_US |
dc.subject | Hybrid memory architecture | en_US |
dc.subject | Non-volatile memory (NVM) | en_US |
dc.subject | Adaptive systems | en_US |
dc.subject | Convex optimization | en_US |
dc.subject | Data storage equipment | en_US |
dc.subject | Design | en_US |
dc.subject | Digital storage | en_US |
dc.subject | Multiprocessing systems | en_US |
dc.subject | Optimization | en_US |
dc.subject | Product design | en_US |
dc.subject | Programmable logic controllers | en_US |
dc.subject | Random access storage | en_US |
dc.subject | Static random access storage | en_US |
dc.subject | Convex modeling | en_US |
dc.subject | Embedded chips | en_US |
dc.subject | Energy delay product | en_US |
dc.subject | Memory design | en_US |
dc.subject | Memory layers | en_US |
dc.subject | Non-volatile memory | en_US |
dc.subject | Power constraints | en_US |
dc.subject | Proposed architectures | en_US |
dc.subject | Memory architecture | en_US |
dc.title | A high-performance hybrid memory architecture for embedded CMPs using a convex optimization model | en_US |
dc.type | Conference Paper | en_US |
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