Design and testing of a microprocessor compatible 128-bit correlator chip

Abstract

In digital synchronous data transmission, synchronization (sync) words are used to mark the beginning of the incoming data stream. Detection of the sync word received from a noisy channel is a difficult problem. One of the optimum solutions to this problem is to use a correlator. A correlator could be implemented with SSI and MSI components on a printed circuit board with the disadvantage of bulkiness. To use it in light-weight equipment such as portable data terminals, it is designed to be implemented as a full custom single VLSI chip. It can be used for 128-bit sync word detection and PRBS generation. Two chips can be cascaded for 256-bit correlation as well as distributed sync words, and inverted or non-inverted sync words can be detected. It is fully programmable by a microprocessor to set the number of tolerable errors in detection and to select the bits of the 128-bit (or 256 bit) input data stream to be used in the correlation and hence, it can be directly connected to a microprocessor as a peripheral device. In designing the correlator chip some Design For Testability methods are used to improve the testability. Especially, scan design and partitioning techniques are applied resulting in a significant decrease in the number of test patterns although these techniques involve an overhead in the overall transistor count only by 1 percent. For functional and timing simulations ESIM and RNL simulators are used, respectively. Test patterns for the registers are generated manually and for testing of the combinational part two programs, gen and check, are written in C programming language. The simulation programs and test pattern generation programs are run on SUN workstations under 4.3 BSD UNIX operating system.