Adaptive thread scheduling in chip multiprocessors

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buir.contributor.authorÖztürk, Özcan
dc.citation.epage1044en_US
dc.citation.issueNumber5-6en_US
dc.citation.spage1014en_US
dc.citation.volumeNumber47en_US
dc.contributor.authorAktürk, İ.en_US
dc.contributor.authorÖztürk, Özcanen_US
dc.date.accessioned2020-02-03T08:03:10Z
dc.date.available2020-02-03T08:03:10Z
dc.date.issued2019
dc.departmentDepartment of Computer Engineeringen_US
dc.description.abstractThe full potential of chip multiprocessors remains unexploited due to architecture oblivious thread schedulers employed in operating systems. We introduce an adaptive cache-hierarchy-aware scheduler that tries to schedule threads in a way that inter-thread contention is minimized. A novel multi-metric scoring scheme is used which specifies L1 cache access characteristics of threads. Scheduling decisions are made based on these multi-metric scores of threads.en_US
dc.identifier.doi10.1007/s10766-019-00637-yen_US
dc.identifier.issn0885-7458en_US
dc.identifier.urihttp://hdl.handle.net/11693/52984en_US
dc.language.isoEnglishen_US
dc.publisherSpringeren_US
dc.relation.isversionofhttps://dx.doi.org/10.1007/s10766-019-00637-yen_US
dc.source.titleInternational Journal of Parallel Programmingen_US
dc.subjectAdaptive schedulingen_US
dc.subjectChip multiprocessorsen_US
dc.subjectInter-thread contentionen_US
dc.subjectMulti-metric scoringen_US
dc.titleAdaptive thread scheduling in chip multiprocessorsen_US
dc.typeArticleen_US

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