Adaptive thread scheduling in chip multiprocessors
Date
2019
Authors
Advisor
Instructor
Source Title
International Journal of Parallel Programming
Print ISSN
0885-7458
Electronic ISSN
Publisher
Springer
Volume
47
Issue
5-6
Pages
1014 - 1044
Language
English
Type
Article
Journal Title
Journal ISSN
Volume Title
Abstract
The full potential of chip multiprocessors remains unexploited due to architecture oblivious thread schedulers employed in operating systems. We introduce an adaptive cache-hierarchy-aware scheduler that tries to schedule threads in a way that inter-thread contention is minimized. A novel multi-metric scoring scheme is used which specifies L1 cache access characteristics of threads. Scheduling decisions are made based on these multi-metric scores of threads.
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Keywords
Adaptive scheduling, Chip multiprocessors, Inter-thread contention, Multi-metric scoring