Ultrathin interfacial layer and pre-gate annealing to suppress virtual gate formation in GaN-based transistors: The impact of trapping and fluorine inclusion

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buir.contributor.authorOdabaşı, Oğuz
buir.contributor.authorGhobadi, Amir
buir.contributor.authorGhobadi, Türkan Gamze Ulusoy
buir.contributor.authorÖzbay, Ekmel
buir.contributor.orcidOdabaşı, Oğuz|0000-0002-2002-1488
buir.contributor.orcidGhobadi, Amir|0000-0002-8146-0361
buir.contributor.orcidGhobadi, Türkan Gamze Ulusoy|0000-0002-7669-1587
buir.contributor.orcidÖzbay, Ekmel|0000-0002-9465-1044
dc.citation.epage1616en_US
dc.citation.issueNumber10en_US
dc.citation.spage1613en_US
dc.citation.volumeNumber43en_US
dc.contributor.authorOdabaşı, Oğuz
dc.contributor.authorGhobadi, Amir
dc.contributor.authorGhobadi, Türkan Gamze Ulusoy
dc.contributor.authorÖzbay, Ekmel
dc.date.accessioned2023-02-28T12:33:47Z
dc.date.available2023-02-28T12:33:47Z
dc.date.issued2022-08-31
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.departmentNanotechnology Research Center (NANOTAM)en_US
dc.description.abstractIn AlGaN/GaN high electron mobility transistors (HEMTs), the long-term operation of the device is adversely affected by threshold voltage ( Vth ) instability and current collapse. In this letter, using structural and electrical analyses, the impact of trapping and fluorine (F) inclusion on the device operation is scrutinized. It is found that SiNx interfacial layer significantly reduced the formation of defects, during the ohmic annealing process. Moreover, the incorporation of F ions into GaN bulk, during the gate etch process, triggers the virtual gate phenomenon. This effect has also been mitigated via the pre-gate annealing (PGA) process. As a result of these modifications, a stable operation with minimized lag performance has been achieved.en_US
dc.description.provenanceSubmitted by Ayça Nur Sezen (ayca.sezen@bilkent.edu.tr) on 2023-02-28T12:33:47Z No. of bitstreams: 1 Ultrathin_interfacial_layer_and_pre-gate_annealing_to_suppress_virtual_gate_formation_in_GaN-based_transistors_The_impact_of_trapping_and_fluorine_inclusion.pdf: 1743650 bytes, checksum: ad32d6a922a908e2a666d1194e3bc27f (MD5)en
dc.description.provenanceMade available in DSpace on 2023-02-28T12:33:47Z (GMT). No. of bitstreams: 1 Ultrathin_interfacial_layer_and_pre-gate_annealing_to_suppress_virtual_gate_formation_in_GaN-based_transistors_The_impact_of_trapping_and_fluorine_inclusion.pdf: 1743650 bytes, checksum: ad32d6a922a908e2a666d1194e3bc27f (MD5) Previous issue date: 2022-08-31en
dc.identifier.doi10.1109/LED.2022.3203291en_US
dc.identifier.eissn1558-0563
dc.identifier.issn0741-3106
dc.identifier.urihttp://hdl.handle.net/11693/111928
dc.language.isoEnglishen_US
dc.publisherInstitute of Electrical and Electronics Engineersen_US
dc.relation.isversionofhttps://doi.org/10.1109/LED.2022.3203291en_US
dc.source.titleIEEE Electron Device Lettersen_US
dc.subjectAlGaN/GaN HEMTen_US
dc.subjectTransistoren_US
dc.subjectPassivationen_US
dc.subject15 lag phenomenaen_US
dc.subjectStabilityen_US
dc.titleUltrathin interfacial layer and pre-gate annealing to suppress virtual gate formation in GaN-based transistors: The impact of trapping and fluorine inclusionen_US
dc.typeArticleen_US

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