High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model
dc.citation.epage | 2610 | en_US |
dc.citation.spage | 2607 | en_US |
dc.contributor.author | Onsori, Salman | en_US |
dc.contributor.author | Asad, Arghavan | en_US |
dc.contributor.author | Raahemifar, K. | en_US |
dc.contributor.author | Fathy, M. | en_US |
dc.coverage.spatial | Montreal, QC, Canada | |
dc.date.accessioned | 2018-04-12T11:49:07Z | |
dc.date.available | 2018-04-12T11:49:07Z | |
dc.date.issued | 2016-05 | en_US |
dc.department | Department of Computer Engineering | en_US |
dc.description | Date of Conference: 22-25 May 2016 | |
dc.description | Conference name: 2016 IEEE International Symposium on Circuits and Systems (ISCAS) | |
dc.description.abstract | In this article, we present a convex optimization model to design a stacked hybrid memory system to improve performance and reduce energy consumption of the chip-multiprocessor (CMP). Our convex model optimizes numbers and placement of SRAM and STT-RAM memories on the memory layer, and efficiently maps applications/threads on cores in the core layer. Power consumption that is the main challenge in the dark silicon era is represented as a power constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D CMP. Experimental results show that the proposed architecture considerably improves the energy-delay product (EDP) and performance of the 3D CMP compared to the Baseline memory design. © 2016 IEEE. | en_US |
dc.description.provenance | Made available in DSpace on 2018-04-12T11:49:07Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 179475 bytes, checksum: ea0bedeb05ac9ccfb983c327e155f0c2 (MD5) Previous issue date: 2016 | en |
dc.identifier.doi | 10.1109/ISCAS.2016.7539127 | en_US |
dc.identifier.uri | http://hdl.handle.net/11693/37724 | en_US |
dc.language.iso | English | en_US |
dc.publisher | IEEE | en_US |
dc.relation.isversionof | http://dx.doi.org/10.1109/ISCAS.2016.7539127 | en_US |
dc.source.title | Proceedings - IEEE International Symposium on Circuits and Systems, 2016 | en_US |
dc.subject | Convex-optimization | en_US |
dc.subject | Dark silicon | en_US |
dc.subject | Embedded chip-multiprocessor (eCMP) | en_US |
dc.subject | Hybrid memory architecture | en_US |
dc.subject | Non-volatile memory (NVM) | en_US |
dc.subject | Power management | en_US |
dc.subject | Convex optimization | en_US |
dc.subject | Data storage equipment | en_US |
dc.subject | Design | en_US |
dc.subject | Digital storage | en_US |
dc.subject | Energy utilization | en_US |
dc.subject | Multiprocessing systems | en_US |
dc.subject | Optimization | en_US |
dc.subject | Power management | en_US |
dc.subject | Product design | en_US |
dc.subject | Random access storage | en_US |
dc.subject | Reconfigurable hardware | en_US |
dc.subject | Silicon | en_US |
dc.subject | Static random access storage | en_US |
dc.subject | Chip multiprocessors | en_US |
dc.subject | Dark silicons | en_US |
dc.subject | Embedded chips | en_US |
dc.subject | Energy delay product | en_US |
dc.subject | Non-volatile memory | en_US |
dc.subject | Optimization modeling | en_US |
dc.subject | Proposed architectures | en_US |
dc.subject | Reduce energy consumption | en_US |
dc.subject | Memory architecture | en_US |
dc.title | High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model | en_US |
dc.type | Conference Paper | en_US |
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