Fault-tolerant irregular topology design method for network-on-chips

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dc.citation.epage634en_US
dc.citation.spage631en_US
dc.contributor.authorTosun, S.en_US
dc.contributor.authorAjabshir V.B.en_US
dc.contributor.authorMercanoglu O.en_US
dc.contributor.authorÖztürk, Özcanen_US
dc.coverage.spatialVerona, Italyen_US
dc.date.accessioned2016-02-08T11:57:41Z
dc.date.available2016-02-08T11:57:41Z
dc.date.issued2014en_US
dc.departmentDepartment of Computer Engineeringen_US
dc.descriptionDate of Conference: 27-29 Aug. 2014en_US
dc.description.abstractAs the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this study, we aim to make faulty chips designed with Network-on-Chip (NoC) communication usable. Specifically, we present a fault-tolerant irregular topology generation method for application specific NoC designs. Designed NoC topology allows a different routing path if there is a link failure on the default routing. We compare fault-tolerant topologies with regular fault-tolerant ring topologies, and non-fault-tolerant application specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. © 2014 IEEE.en_US
dc.description.provenanceMade available in DSpace on 2016-02-08T11:57:41Z (GMT). No. of bitstreams: 1 bilkent-research-paper.pdf: 70227 bytes, checksum: 26e812c6f5156f83f0e77b261a471b5a (MD5) Previous issue date: 2014en
dc.identifier.doi10.1109/DSD.2014.13en_US
dc.identifier.urihttp://hdl.handle.net/11693/27607
dc.language.isoEnglishen_US
dc.publisherIEEEen_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/DSD.2014.13en_US
dc.source.title2014 17th Euromicro Conference on Digital System Designen_US
dc.subjectEnergyen_US
dc.subjectFault toleranceen_US
dc.subjectNetwork-on-Chipen_US
dc.subjectTopologyen_US
dc.subjectBenchmarkingen_US
dc.subjectDesignen_US
dc.subjectDistributed computer systemsen_US
dc.subjectEnergy utilizationen_US
dc.subjectFault toleranceen_US
dc.subjectFault tolerant computer systemsen_US
dc.subjectMicroprocessor chipsen_US
dc.subjectNetwork-on-chipen_US
dc.subjectRoutersen_US
dc.subjectServersen_US
dc.subjectTopologyen_US
dc.subjectVLSI circuitsen_US
dc.subjectApplication specificen_US
dc.subjectEnergyen_US
dc.subjectFault-tolerant applicationsen_US
dc.subjectIntegrated circuits (ICs)en_US
dc.subjectIrregular topologyen_US
dc.subjectMultimedia benchmarksen_US
dc.subjectNetwork-on-chip(NoC)en_US
dc.subjectSingle-link failuresen_US
dc.subjectIntegrated circuit designen_US
dc.titleFault-tolerant irregular topology design method for network-on-chipsen_US
dc.typeConference Paperen_US

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