Controller redesign for delay margin improvement

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buir.contributor.authorÖzbay, Hitay
dc.citation.epage108790-8en_US
dc.citation.spage108790-1en_US
dc.citation.volumeNumber113en_US
dc.contributor.authorGündeş, A. N.
dc.contributor.authorÖzbay, Hitay
dc.date.accessioned2021-02-20T18:43:09Z
dc.date.available2021-02-20T18:43:09Z
dc.date.issued2020-01
dc.departmentDepartment of Electrical and Electronics Engineeringen_US
dc.description.abstractTwo important design objectives in feedback control are steady-state error minimization and delaymargin maximization. For many practical systems it is not possible to have infinite delay margin andzero steady state error for unit step reference input. This paper proposes a re-design method forcontrollers initially designed to satisfy the steady-state error requirement. The objective is to makestructural changes in the controller so that a lower bound of the delay margin is improved withoutaffecting the steady-state error. The order of the new controller is (ν+1) higher than the order of theoriginal controller, whereνis the number of unstable poles of the plant.en_US
dc.embargo.release2022-01-09
dc.identifier.doi10.1016/j.automatica.2019.108790en_US
dc.identifier.issn0005-1098
dc.identifier.urihttp://hdl.handle.net/11693/75519
dc.language.isoEnglishen_US
dc.publisherElsevieren_US
dc.relation.isversionofhttps://doi.org/10.1016/j.automatica.2019.108790en_US
dc.source.titleAutomaticaen_US
dc.subjectTime delayen_US
dc.subjectStability marginsen_US
dc.subjectStability marginsen_US
dc.subjectLinear systemsen_US
dc.subjectStabilization Interpolationen_US
dc.titleController redesign for delay margin improvementen_US
dc.typeArticleen_US

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