Controller redesign for delay margin improvement

Two important design objectives in feedback control are steady-state error minimization and delaymargin maximization. For many practical systems it is not possible to have infinite delay margin andzero steady state error for unit step reference input. This paper proposes a re-design method forcontrollers initially designed to satisfy the steady-state error requirement. The objective is to makestructural changes in the controller so that a lower bound of the delay margin is improved withoutaffecting the steady-state error. The order of the new controller is (ν+1) higher than the order of theoriginal controller, whereνis the number of unstable poles of the plant.