Browsing by Subject "Very large scale integration"

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Open Access
Design and implementation of a general purpose VLSI median filter unit and its applications
(IEEE, 1989) Karaman, Mustafa; Onural, Levent; Atalar, Abdullah
A VLSI median filter unit has been designed and implemented in 3-μ m M2 CMOS, using full-custom VLSI design techniques. The unit consists of two single-chip median filters, one extensible and one real-time. The chips are bit-level pipelined systolic structures based on odd/even transposition sorting. The extensible chip is designed for applications requiring variable window sizes and variable word-lengths, whereas the other one is for real-time applications. Various median filtering techniques are easily realized by using the designed chips together with reasonable external hardware.
Open Access
A new method for nonlinear circuit simulation in time domain: NOWE
(Institute of Electrical and Electronics Engineers, 1996-03) Ocalı, O.; Tan, M. A.; Atalar, Abdullah
A new method for the time-domain solution of general nonlinear dynamic circuits is presented. In this method, the solutions of the state variables are computed by using their time derivatives up to some order at the initial time instant. The computation of the higher order derivatives is equivalent to solving the same linear circuit for various sets of dc excitations. Once the time derivatives of the state variables are obtained, an approximation to the solution can be found as a polynomial rational function of time. The time derivatives of the approximation at the initial time instant are matched to those of the exact solution. This method is promising in terms of execution speed, since it can achieve the same accuracy as the trapezoidal approximation with much smaller number of matrix inversions.
Open Access
A VLSI receive beamformer for digital ultrasound imaging
(IEEE, 1992-03) Karaman, Mustafa; Kolağasıoğlu, Ertuğrul; Atalar, Abdullah
A VLSI architecture for real-time digital receive beamforming in phased array ultrasound imaging is proposed. The architecture is an inverse binary tree like structure with N stages where N is the number of array elements. The sampled signals from the phased array channels are coherently added in a pairwise manner within the stages of the architecture in a pipelined data flow scheme. The storage requirement for the synchronization of the asynchronously received samples corresponding to a focal point is significantly reduced. The architecture is modular and has a regular communication scheme which make the VLSI implementation rather easy and straightforward.