Design and implementation of a general purpose VLSI median filter unit and its applications
A VLSI median filter unit has been designed and implemented in 3-μ m M2 CMOS, using full-custom VLSI design techniques. The unit consists of two single-chip median filters, one extensible and one real-time. The chips are bit-level pipelined systolic structures based on odd/even transposition sorting. The extensible chip is designed for applications requiring variable window sizes and variable word-lengths, whereas the other one is for real-time applications. Various median filtering techniques are easily realized by using the designed chips together with reasonable external hardware.