Browsing by Subject "Successive cancellation"

Now showing 1 - 4 of 4

Open Access
Lossless polar compression of g-ary sources
(IEEE, 2013) Çaycı, Semih; Arıkan, Orhan
In this paper, lossless polar compression of g-ary memoryless sources in the noiseless setting is investigated. Polar compression scheme for binary memoryless sources, introduced by Cronie and Korada, is generalized to sources over prime-size alphabets. In order to reduce the average codeword length, a compression scheme based on successive cancellation list decoding is proposed. Also, a specific configuration for the compression of correlated sources is considered, and it is shown that the introduced polar compression schemes achieve the corner point of the admissible rate region. Based on this result, proposed compression schemes are extended to arbitrary finite source alphabets by using a layered approach. © 2013 IEEE.
Open Access
On the rate of channel polarization
(IEEE, 2009-06-07) Arıkan, Erdal; Telatar, E.
A bound is given on the rate of channel polarization. As a corollary, an earlier bound on the probability of error for polar coding is improved. Specifically, it is shown that, for any binary-input discrete memoryless channel W with symmetric capacity I(W) and any rate R < I(W), the polar-coding blockerror probability under successive cancellation decoding satisfies Pe(N;R) ≥ 2-Nβ for any β > 1/2 when the block-length N is large enough. © 2009 IEEE.
Open Access
Successive cancellation decoding of polar codes for the two-user binary-input MAC
(IEEE, 2013) Önay, Saygun
This paper describes a successive cancellation decoder of polar codes for the two-user binary-input multi-access channel that achieves the full admissible rate region. The polar code for the channel is generated from monotone chain rule expansions of mutual information terms.
Open Access
A two phase successive cancellation decoder architecture for polar codes
(IEEE, 2013) Pamuk, Alptekin; Arıkan, Erdal
We propose a two-phase successive cancellation (TPSC) decoder architecture for polar codes that exploits the array-code property of polar codes by breaking the decoding of a length-TV polar code into a series of length-√ L decoding cycles. Each decoding cycle consists of two phases: a first phase for decoding along the columns and a second phase for decoding along the rows of the code array. The reduced decoder size makes it more affordable to implement the core decoder logic using distributed memory elements consisting of flip-flops (FFs), as opposed to slower random access memory (RAM), leading to a speed up in clock frequency. To minimize the circuit complexity, a single decoder unit is used in both phases with minor modifications. The re-use of the same decoder module makes it necessary to recall certain internal decoder state variables between decoding cycles. Instead of storing the decoder state variables in RAM, the decoder discards them and calculates them again when needed. Overall, the decoder has O(√ L) circuit complexity excluding RAM, and a latency of approximately 2.57V. A RAM of size O(N) is needed for storing the channel log-likelihood variables and the decoder decision variables. As an example of the proposed method, a length N = 214 bit polar code is implemented in an FPGA and the synthesis results are compared with a previously reported FPGA implementation. The results show that the proposed architecture has lower complexity, lower memory utilization with higher throughput, and a clock frequency that is less sensitive to code length. © 2013 IEEE.