Browsing by Subject "Semiconductor storage"
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Item Open Access Memristive behavior in a junctionless flash memory cell(American Institute of Physics Inc., 2015) Orak, I.; Ürel, M.; Bakan, G.; Dana, A.We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO2 as the tunnel dielectric, AI2O3 as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits the pinched hysteresis of a memristor and in the unoptimized device, R off/R on ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts Roff/Ron ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 106 s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.Item Open Access Thin-film ZnO charge-trapping memory cell grown in a single ALD step(Institute of Electrical and Electronics Engineers, 2012-10-26) Oruc, F. B.; Cimen, F.; Rizk, A.; Ghaffari, M.; Nayfeh, A.; Okyay, Ali KemalA thin-film ZnO-based single-transistor memory cell with a gate stack deposited in a single atomic layer deposition step is demonstrated. Thin-film ZnO is used as channel material and charge-trapping layer for the first time. The extracted mobility and subthreshold slope of the thin-film device are 23 cm2/V · s and 720 mV/dec, respectively. The memory effect is verified by a 2.35-V hysteresis in the $I\rm drain- $V\rm gate curve. Physics-based TCAD simulations show very good agreement with the experimental results providing insight to the charge-trapping physics.