Browsing by Subject "Retention characteristics"

Now showing 1 - 5 of 5

Open Access
Charge Trapping Memory with 2.85-nm Si-Nanoparticles Embedded in HfO2
(ECS, 2015-05) El-Atab, N.; Turgut, Berk Berkan; Okyay, Ali Kemal; Nayfeh, A.
In this work, the effect of embedding 2.85-nm Si-nanoparticles charge trapping layer in between double layers of high-κ Al2O3/HfO2 oxides is studied. Using high frequency (1 MHz) C-Vgate measurements, the memory showed a large memory window at low program/erase voltages due to the charging of the Si-nanoparticles. The analysis of the C-V characteristics shows that mixed charges are being stored in the Si-nanoparticles where electrons get stored during the program operation while holes dominate in the Si-nanoparticles during the erase operation. Moreover, the retention characteristic of the memory is studied by measuring the memory hysteresis in time. The obtained retention characteristic (35.5% charge loss in 10 years) is due to the large conduction and valence band offsets between the Si-nanoparticles and the Al2O3/HfO2 tunnel oxide. The results show that band engineering is essential in future low-power non-volatile memory devices. In addition, the results show that Si-nanoparticles are promising in memory applications.
Open Access
Cubic-phase zirconia nano-island growth using atomic layer deposition and application in low-power charge-trapping nonvolatile-memory devices
(Institute of Physics Publishing Ltd., 2017) El-Atab, N.; Ulusoy, T. G.; Ghobadi, A.; Suh, J.; Islam, R.; Okyay, Ali Kemal; Saraswat, K.; Nayfeh, A.
The manipulation of matter at the nanoscale enables the generation of properties in a material that would otherwise be challenging or impossible to realize in the bulk state. Here, we demonstrate growth of zirconia nano-islands using atomic layer deposition on different substrate terminations. Transmission electron microscopy and Raman measurements indicate that the nano-islands consist of nano-crystallites of the cubic-crystalline phase, which results in a higher dielectric constant (κ ∼ 35) than the amorphous phase case (κ ∼ 20). X-ray photoelectron spectroscopy measurements show that a deep quantum well is formed in the Al2O3/ZrO2/Al2O3 system, which is substantially different to that in the bulk state of zirconia and is more favorable for memory application. Finally, a memory device with a ZrO2 nano-island charge-trapping layer is fabricated, and a wide memory window of 4.5 V is obtained at a low programming voltage of 5 V due to the large dielectric constant of the islands in addition to excellent endurance and retention characteristics.
Open Access
Graphene Nanoplatelets Embedded in HfO2 for MOS Memory
(Electrochemical Society Inc., 2015) El-Atab, N.; Turgut, Berk Berkan; Okyay, Ali Kemal; Nayfeh, A.
In this work, a MOS memory with graphene nanoplatelets charge trapping layer and a double layer high-κ Al2O3/HfO2 tunnel oxide is demonstrated. Using C-Vgate measurements, the memory showed a large memory window at low program/erase voltages. The analysis of the C-V characteristics shows that electrons are being stored in the graphene-nanoplatelets during the program operation. In addition, the retention characteristic of the memory is studied by plotting the hysteresis measurement vs. time. The measured excellent retention characteristic (28.8% charge loss in 10 years) is due to the large electron affinity of the graphene. The analysis of the plot of the energy band diagram of the MOS structure further proves its good retention characteristic. Finally, the results show that such graphene nanoplatelets are promising in future low-power non-volatile memory devices.
Open Access
Low power zinc-oxide based charge trapping memory with embedded silicon nanoparticles via poole-frenkel hole emission
(2014) El-Atab, N.; Ozcan, A.; Alkis, S.; Okyay, Ali Kemal; Nayfeh, A.
A low power zinc-oxide (ZnO) charge trapping memory with embedded silicon (Si) nanoparticles is demonstrated. The charge trapping layer is formed by spin coating 2 nm silicon nanoparticles between Atomic Layer Deposited ZnO steps. The threshold voltage shift (ΔVt) vs. programming voltage is studied with and without the silicon nanoparticles. Applying -1 V for 5 s at the gate of the memory with nanoparticles results in a ΔVt of 3.4 V, and the memory window can be up to 8 V with an excellent retention characteristic (>10 yr). Without nanoparticles, at -1 V programming voltage, the ΔVt is negligible. In order to get ΔVt of 3.4 V without nanoparticles, programming voltage in excess of 10 V is required. The negative voltage on the gate programs the memory indicating that holes are being trapped in the charge trapping layer. In addition, at 1 V the electric field across the 3.6 nm tunnel oxide is calculated to be 0.36 MV/cm, which is too small for significant tunneling. Moreover, the ΔVt vs. electric field across the tunnel oxide shows square root dependence at low fields (E 1 MV/cm) and a square dependence at higher fields (E > 2.7 MV/cm). This indicates that Poole-Frenkel Effect is the main mechanism for holes emission at low fields and Phonon Assisted Tunneling at higher fields. © 2014 AIP Publishing LLC.
Open Access
Two-nanometer laser synthesized Si-nanoparticles for low power memory applications
(Springer International Publishing, 2016) El-Atab, N.; Okyay, Ali Kemal; Nayfeh, A.
Current flash memory devices are expected to face two major challenges in the near future: density and voltage scaling. The density of the memory is related to the gate length scaling which is constrained by the gate stack, namely, the tunnel oxide thickness. In fact, the gate length is required to be commensurate with the gate stack in order to maintain a good gate control and to avoid short channel effects. However, in conventional flash memories, the tunnel oxide thickness has a lower limit of 6-7 nm (depending on NOR or NAND structure) in order to avoid back-tunneling and thus leakage of charges which destroys the necessary retention characteristic of the memory (>10 years). The second problem which needs to be solved is the high program and erase operating voltages. Once again, the limitation to operating voltage scaling is the inability to reduce gate stack thickness. Therefore, it is imperative to find novel structures and materials to be incorporated in the memory cells which would allow tunnel oxide and voltage scaling. In this study, MOSFET- and MOSCAP-based memory devices are investigated along with the use of 2-nm silicon nanoparticles (Si-NPs) for charge storage. Atomic layer deposition is used to deposit the active layer of the memory and the spin coating is performed to deliver the Si-nanoparticles across the sample.