Browsing by Subject "Phase Noise"

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    Estimation of receiver sampling clock timing impurity impact on channel orthogonality in OFDM based communication systems
    (2009) Tanyeri, H. Onur
    The growing need for high-speed wireless communication systems has led communication engineers to design and implement communication systems at higher frequencies where more bandwidth is available, use digital modulation schemes with more complex constellations and place carriers closer together with little guard-band in the pursuit of designing communication systems closer to the channel capacity. These new designs have placed tighter constraints on the performance of oscillators and timing devices of transceivers. In this work, the effects of timing clock jitter on the receiver Analog-to-Digital Converter (ADC) of Orthogonal Frequency Division Multiplexing (OFDM) based communication systems are examined and Inter-Carrier Interference (ICI) effects are quantified in order to prevent unnecessary over designs in OFDM ADC circuitry. In this respect, a simulation tool that synthesizes jitter processes with defined spectral characteristics is prepared. The generated jitter processes are utilized in an OFDM simulation tool that quantifies the ICI levels caused by receiver ADC sampling jitter. Using these two tools, ICI levels of certain OFDM systems are examined and guidelines for OFDM ADC circuitry design are proposed.
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    X-band low phase noise mmic vco & high power mmic spdt design
    (2014) Osmanoğlu, Sinan
    Generally the tuning bandwidth (BW) of a VCO is smaller than the tuning BW of the resonant circuit itself. Using proper components with right topology can handle this problem. In order to overcome this problem and improve the tuning BW of the VCO, common-base inductive feedback topology with Gallium Arsenide (GaAs) Heterojunction Bipolar Transistor (HBT) is used and an optimized topology for tank circuit is selected to minimize the effect of bandwidth limiting components. Designed VCO with this topology achived -117 dBc/Hz at 1 MHz offset phase noise with 9-13 dBm output power between 8.8-11.4 GHz band. Second part of the thesis composed of Single Pole Double Throw (SPDT) RF Switch design. From mesa resistors to SPDT fabrication, everything is fabricated using Bilkent University NANOTAM Gallium Nitride (GaN) on Silicon Carbide (SiC) process. Switching HEMTs are fabricated to generate a model to design SPDTs and the final design works between DC-12 GHz with less than 1.4 dB insertion loss (IL), -20 dB isolation and 14.5 dB return loss (RL) at worst case. The power handling of the switches are better than 40 dBm at output with 0.2 dB compression, which is measured with continuous wave (CW) signal at 10 GHz.