Estimation of receiver sampling clock timing impurity impact on channel orthogonality in OFDM based communication systems

Abstract

The growing need for high-speed wireless communication systems has led communication engineers to design and implement communication systems at higher frequencies where more bandwidth is available, use digital modulation schemes with more complex constellations and place carriers closer together with little guard-band in the pursuit of designing communication systems closer to the channel capacity. These new designs have placed tighter constraints on the performance of oscillators and timing devices of transceivers. In this work, the effects of timing clock jitter on the receiver Analog-to-Digital Converter (ADC) of Orthogonal Frequency Division Multiplexing (OFDM) based communication systems are examined and Inter-Carrier Interference (ICI) effects are quantified in order to prevent unnecessary over designs in OFDM ADC circuitry. In this respect, a simulation tool that synthesizes jitter processes with defined spectral characteristics is prepared. The generated jitter processes are utilized in an OFDM simulation tool that quantifies the ICI levels caused by receiver ADC sampling jitter. Using these two tools, ICI levels of certain OFDM systems are examined and guidelines for OFDM ADC circuitry design are proposed.