Browsing by Subject "Mapping"

Now showing 1 - 20 of 28

Open Access
The aid of colour on spatial navigation: A study in a virtual hospital environment
(ACM, 2016) Kumaoğlu, Özge; Olguntürk, Nilgün
The aim of this study is to explore the effects of colour as visuo-spatial cue on spatial navigation and developing a cognitive map in elderly in a simulated virtual hospital environment. The study further purports to explore whether it is possible to improve elders' spatial navigation and cognitive mapping performances as well as younger-aged group, by the aid of coloured visuo-spatial cues. © 2016 ACM.
Open Access
Application mapping algorithms for mesh-based network-on-chip architectures
(Springer New York LLC, 2015-03) Tosun, S.; Ozturk, O.; Ozkan, E.; Ozen, M.
Due to shrinking technology sizes, more and more processing elements and memory blocks are being integrated on a single die. However, traditional communication infrastructures (e.g., bus or point-to-point) cannot handle the synchronization problems of these large systems. Using network-on-chip (NoC) is a step towards solving this communication problem. Energy- and communication-efficient application mapping is a previously studied problem for mesh-based NoC architectures; however, there is still need for intelligent mapping algorithms since current algorithms either take too much running time or do not determine accurate results. To fill this need, in this study, we propose two mapping algorithms (one based on simulated annealing and one based on genetic algorithm) for energy- and communication-aware mapping problems of mesh-based NoC architectures. We compare these two algorithms with an integer linear programming-based method and a heuristic method using several multimedia and synthetic benchmarks.
Open Access
Architecture framework for mapping parallel algorithms to parallel computing platforms
(CEUR-WS, 2013) Tekinerdogan, Bedir; Arkin, E.
Mapping parallel algorithms to parallel computing platforms requires several activities such as the analysis of the parallel algorithm, the definition of the logical configuration of the platform, and the mapping of the algorithm to the logical configuration platform. Unfortunately, in current parallel computing approaches there does not seem to be precise modeling approaches for supporting the mapping process. The lack of a clear and precise modeling approach for parallel computing impedes the communication and analysis of the decisions for supporting the mapping of parallel algorithms to parallel computing platforms. In this paper we present an architecture framework for modeling the various views that are related to the mapping process. An architectural framework organizes and structures the proposed architectural viewpoints. We propose five coherent set of viewpoints for supporting the mapping of parallel algorithms to parallel computing platforms. We illustrate the architecture framework for the mapping of array increment algorithm to the parallel computing platform. Copyright © 2013 for the individual papers by the papers' authors.
Open Access
Decalcomania, mapping and mimesis
(University of Nebraska Press, 2005) Aracagök, Z.
Open Access
Dynamic thread and data mapping for NoC based CMPs
(IEEE, 2009-07) Kandemir, M.; Öztürk, Özcan; Muralidhara, S. P.
Thread mapping and data mapping are two important problems in the context of NoC (network-on-chip) based CMPs (chip multiprocessors). While a compiler can determine suitable mappings for data and threads, such static mappings may not work well for multithreaded applications that go through different execution phases during their execution, each phase with potentially different data access patterns than others. Instead, a dynamic mapping strategy, if its overheads can be kept low, may be a more promising option. In this work, we present dynamic (runtime) thread and data mappings for NoC based CMPs. The goal of these mappings is to reduce the distance between the location of the core that requests data and the core whose local memory contains that requested data. In our experiments, we evaluate our proposed thread mapping and data mapping in isolation as well as in an integrated manner. Copyright 2009 ACM.
Open Access
Effective kernel mapping for OpenCL applications in heterogeneous platforms
(Institute of Electrical and Electronics Engineers, 2012-09) Albayrak, Ömer Erdil; Aktürk, İsmail; Öztürk, Özcan
Many core accelerators are being deployed in many systems to improve the processing capabilities. In such systems, application mapping need to be enhanced to maximize the utilization of the underlying architecture. Especially in GPUs mapping becomes critical for multi-kernel applications as kernels may exhibit different characteristics. While some of the kernels run faster on GPU, others may refer to stay in CPU due to the high data transfer overhead. Thus, heterogeneous execution may yield to improved performance compared to executing the application only on CPU or only on GPU. In this paper, we propose a novel profiling-based kernel mapping algorithm to assign each kernel of an application to the proper device to improve the overall performance of an application. We use profiling information of kernels on different devices and generate a map that identifies which kernel should run on where to improve the overall performance of an application. Initial experiments show that our approach can effectively map kernels on CPU and GPU, and outperforms to a CPU-only and GPU-only approach. © 2012 IEEE.
Open Access
Efficient parallel spatial subdivision algorithm for object-based parallel ray tracing
(Pergamon Press, 1994) Aykanat, Cevdet; İşler, V.; Özgüç, B.
Parallel ray tracing of complex scenes on multicomputers requires the distribution of both computation and scene data to the processors. This is carried out during preprocessing and usually consumes too much time and memory. The paper presents an efficient parallel subdivision algorithm that decomposes a given scene into rectangular regions adaptively and maps the resultant regions to the node processors of a multicomputer. The proposed algorithm uses efficient data structures to identify the splitting planes quickly. Furthermore the mapping of the regions and the objects to the node processors is performed while parallel spatial subdivision proceeds. The proposed algorithm is implemented on an Intel iPSC/2 hypercube multicomputer and promising results have been obtained. © 1994.
Open Access
Fault-tolerant topology generation method for application-specific network-on-chips
(Institute of Electrical and Electronics Engineers, 2015) Tosun, S.; Ajabshir, V. B.; Mercanoglu, O.; Ozturk, O.
As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this paper, we aim to make faulty chips designed with network-on-chip (NoC) communication usable. Specifically, we present fault-tolerant irregular topology-generation method for application-specific NoC designs. Designed NoC topology allows different routing path if there is a link failure on the default routing path. Additionally, we present a simulated annealing-based application mapping algorithm aiming to minimize total energy consumption of the NoC design. We compare fault-tolerant topologies with nonfault-tolerant application-specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. Our results demonstrate that our method is able to determine fault-tolerant topologies with negligible area increase and better energy values.
Open Access
ILP formulation and heuristic method for energy-aware application mapping on 3D-NoCs
(Springer, 2020-07-01) Nalcı, Y.; Kullu, P.; Tosun, S.; Öztürk, Özcan
The rapid increase in the number of cores on chips forced the designers to invent new communication methods such as Network-on-Chip (NoC) paradigm. Advances in integrated circuit fabrications even allowed three-dimensional NoC (3D-NoC) implementations. 3D-NoCs have more advantages than their 2D counterparts such as lower area, higher throughput, better performance, and less energy consumption. However, they lack the design automation algorithms. An important design problem for a given application is mapping it on a 3D-NoC topology. In this paper, we present an integer linear programming (ILP) formulation and a novel heuristic algorithm, called CastNet3D, for application mapping onto mesh-based 3D-NoCs with energy minimization being the objective. The algorithm tries to utilize vertical links for communicating nodes as much as possible. Vertical links are shorter than horizontal ones; therefore, they are faster and consume less energy. We compared CastNet3D against ILP in terms of energy consumption and execution time on several benchmarks. Our results show that CastNet3D obtains close to optimum results in much shorter time frames.
Open Access
An ILP formulation for application mapping onto Network-on-Chips
(IEEE, 2009) Tosun, S.; Öztürk, Özcan; Ozen, M.
Ever shrinking technologies in VLSI era made it possible to place several modules onto a single die. However, the need for the new communication methods has also increased dramatically since traditional bus-based systems suffer from signal propagation delays, signal integrity, and scalability. Network-on-Chip (NoC) is the biggest step towards the communication bottleneck of System-on-Chip (SoC) architectures. In this paper, we present an Integer Linear Programming (ILP) formulation for application mapping onto mesh based Network-on-Chips to minimize the energy consumption of the system. The proposed method obtains optimal or close to optimal results within the given computation time limit. We also experimentally investigate the impact of the size of the mesh architecture on the application mapping and total communication. ©2009 IEEE.
Open Access
Ionolab grubunun iyonküre uzaktan algılama ve 2-b görüntüleme çalışmaları
(IEEE, 2014-04) Arıkan, F.; Toker, C.; Sezen, U.; Deviren, M. N.; Çilibaş, O.; Arıkan, Orhan
Bu çalışmada, IONOLAB grubunun son 10 yıldır iyonküre uzaktan algılaması ve 2-B görüntüleme çalışmaları özetlenecektir. TÜBİTAK EEEAG 105E171 ve 109E055 projelerinde, çift frekanslı Yerküresel Konumlama Sistemi (YKS) alıcılarının sözde menzil ve faz gecikmesi kayıtlarından özgün Toplam Elektron İçeriği (TEİ) kestirim yöntemi IONOLAB-TEC geliştirilmiştir. Önemli bir Uzay Havası hizmeti olarak www.ionolab.org sitesinden tüm araştırmacılara açılan IONOLAB-TEC, dünyada ilk ve tek gürbüz, güvenilir ve hassas tek istasyon için TEİ kestirimleri yapabilmektedir. Uzayda ve zamanda seyrek YKS-TEİ kestirimlerinin bölgesel ve yerküresel aradeğerlemesi için çalışmalar yapılmış ve Türkiye üzerindeki TUSAGA-Aktif istasyon ağından IONOLAB-TEC yöntemi ile elde edilen Toplam Elektron İçeriği (TEİ) kestirimleri kullanılarak otomatik yüksek çözünürlüklü 2-B TEİ görüntüleri elde edilmiştir. IRI-Plas iyonküre iklimsel modeli altyapısıyla literatürde ilk kez hızlı ve gürbüz elektron yoğunluğu dağılımları elde edilmiş ve iyonküre model parametreleri özgün aradeğerleme ile birleştirilmiştir. www.ionolab.org sitesinde iyonküre kritik frekans ve yükseklik haritaları sunulmaktadır. IONOLAB grubunun bu önemli katkıları TÜBİTAK EEEAG 112E568 projesi kapsamında devam etmektedir.
Open Access
Line segment based range scan matching without pose information for indoor environments
(2008) Yakın, İskender
A mobile robot exploring an unknown environment often needs to keep track of its pose through its sensors. Range scan matching is a way of computing the pose difference of a robot at two different locations on the navigation path by finding common features observed in range sensor readings recorded at these locations. In this thesis, we introduce a new algorithm which computes this pose difference by matching common line segments extracted from two laser range scans taken from two different but unknown poses. In this algorithm, matching is performed by exploiting invariant geometric relations among line segments. The use of line segments instead of range points also reduces the computational complexity of determining the pose difference between two distinct scans. Compared to other scan matching algorithms, our method presents a powerful means for global scan matching, map building, place recognition, loop closing and multirobot mapping, all in real-time.
Open Access
Mapping and FPGA global routing using Mean Field Annealing
(1994) Haritaoğlu, İsmail
Mean Field Annealing algorithm which was proposed for solving combinatorial opimization problems combines the properties of neural networks and Simulated Annealing. In this thesis, MFA is formulated for mapping problem in parallel processing and global rouing problem in physical design automation of Field Programmable Gate Arrays (FPGAs). A new Mean Field Annealing (MFA) formulation is proposed for the mapping problem for mesh-connected and hypercube architectures. The proposed MFA heuristic exploits the conventional routing scheme used in mesh and hypercube interconnection topologies to introduce an efficient encoding scheme. An efficient implementation scheme which decreases the complexity of the proposed algorithm by asymptotical factors is also developed. Experimental results also show that the proposed MFA heuristic approaches the speed performance of the fast Kernighan-Lin heuristic while approaching the solution quality of the powerful simulated annealing heuristic. Also, we propose an order-independent global routing algorithm for SRAM type FPGAs based on Mean Field Annealing The performance of the proposed global algorithm is evaluated in comparison with LocusRoute global router on ACM/SIGDA Design Automation benchmarks. Experimental results indicate that the proposed MFA heuristic peforms better than the LocusRoute.
Open Access
Mapping theory: production of knowledge in theory of architecture in Turkey
(ITU Faculty of Architecture, 2019-07) Anay, H.; Acar, Yiğit; Özten, Ü.; Özten Anay, M.
The study presents a ‘mapping’ of the production of knowledge in the field of theory of architecture in Turkey in the last two decades. The study is based on 307 dissertations produced in Turkey between 1995-2015. Through text mining and unstructured data analysis methods, the research suggests a taxonomy of research in the field. Conceptualizing its method as ‘cartography of knowledge’ the study aims to document the current state of PhD. research in theory of architecture in Turkish context and provide insights about research trajectories in the field.
Open Access
Model-driven approach for supporting the mapping of parallel algorithms to parallel computing platforms
(Springer, Berlin, Heidelberg, 2013) Arkin, E.; Tekinerdogan, Bedir; Imre, K.M.
The trend from single processor to parallel computer architectures has increased the importance of parallel computing. To support parallel computing it is important to map parallel algorithms to a computing platform that consists of multiple parallel processing nodes. In general different alternative mappings can be defined that perform differently with respect to the quality requirements for power consumption, efficiency and memory usage. The mapping process can be carried out manually for platforms with a limited number of processing nodes. However, for exascale computing in which hundreds of thousands of processing nodes are applied, the mapping process soon becomes intractable. To assist the parallel computing engineer we provide a model-driven approach to analyze, model, and select feasible mappings. We describe the developed toolset that implements the corresponding approach together with the required metamodels and model transformations. We illustrate our approach for the well-known complete exchange algorithm in parallel computing. © 2013 Springer-Verlag.
Open Access
Model-driven transformations for mapping parallel algorithms on parallel computing platforms
(MDHPCL, 2013) Arkin, E.; Tekinerdoğan, Bedir
One of the important problems in parallel computing is the mapping of the parallel algorithm to the parallel computing platform. Hereby, for each parallel node the corresponding code for the parallel nodes must be implemented. For platforms with a limited number of processing nodes this can be done manually. However, in case the parallel computing platform consists of hundreds of thousands of processing nodes then the manual coding of the parallel algorithms becomes intractable and error-prone. Moreover, a change of the parallel computing platform requires considerable effort and time of coding. In this paper we present a model-driven approach for generating the code of selected parallel algorithms to be mapped on parallel computing platforms. We describe the required platform independent metamodel, and the model-to-model and the model-to-text transformation patterns. We illustrate our approach for the parallel matrix multiplication algorithm. Copyright © 2013 for the individual papers by the papers' authors.
Open Access
Nanopore sequencing technology and tools for genome assembly: computational analysis of the current state, bottlenecks and future directions
(Oxford University Press, 2018-04) Cali, D. S.; Kim, J. S.; Ghose, S.; Alkan, Can; Mutlu, O.
Nanopore sequencing technology has the potential to render other sequencing technologies obsolete with its ability to generate long reads and provide portability. However, high error rates of the technology pose a challenge while generating accurate genome assemblies. The tools used for nanopore sequence analysis are of critical importance, as they should overcome the high error rates of the technology. Our goal in this work is to comprehensively analyze current publicly available tools for nanopore sequence analysis to understand their advantages, disadvantages and performance bottlenecks. It is important to understand where the current tools do not perform well to develop better tools. To this end, we (1) analyze the multiple steps and the associated tools in the genome assembly pipeline using nanopore sequence data, and (2) provide guidelines for determining the appropriate tools for each step. Based on our analyses, we make four key observations: (1) the choice of the tool for basecalling plays a critical role in overcoming the high error rates of nanopore sequencing technology. (2) Read-to-read overlap finding tools, GraphMap and Minimap, perform similarly in terms of accuracy. However, Minimap has a lower memory usage, and it is faster than GraphMap. (3) There is a trade-off between accuracy and performance when deciding on the appropriate tool for the assembly step. The fast but less accurate assembler Miniasm can be used for quick initial assembly, and further polishing can be applied on top of it to increase the accuracy, which leads to faster overall assembly. (4) The state-of-the-art polishing tool, Racon, generates high-quality consensus sequences while providing a significant speedup over another polishing tool, Nanopolish. We analyze various combinations of different tools and expose the trade-offs between accuracy, performance, memory usage and scalability. We conclude that our observations can guide researchers and practitioners in making conscious and effective choices for each step of the genome assembly pipeline using nanopore sequence data. Also, with the help of bottlenecks we have found, developers can improve the current tools or build new ones that are both accurate and fast, to overcome the high error rates of the nanopore sequencing technology.
Open Access
Objective error criterion for evaluation of mapping accuracy based on sensor time-of-flight measurements
(2008) Barshan, B.
An objective error criterion is proposed for evaluating the accuracy of maps of unknown environments acquired by making range measurements with different sensing modalities and processing them with different techniques. The criterion can also be used for the assessment of goodness of fit of curves or shapes fitted to map points. A demonstrative example from ultrasonic mapping is given based on experimentally acquired time-of-flight measurements and compared with a very accurate laser map, considered as absolute reference. The results of the proposed criterion are compared with the Hausdorff metric and the median error criterion results. The error criterion is sufficiently general and flexible that it can be applied to discrete point maps acquired with other mapping techniques and sensing modalities as well.
Open Access
Performance evaluation of ultrasonic arc map processing techniques by active snake contours
(2008) Altun, K.; Barshan, B.
Active snake contours are considered for representing the maps of an environment obtained by different ultrasonic arc map (UAM) processing techniques efficiently. The mapping results are compared with the actual map of the room obtained with a very accurate laser system. This technique is a convenient way to represent and compare the map points obtained with different techniques among themselves, as well as with an absolute reference. It is also applicable to map points obtained with other mapping techniques. © 2008 Springer-Verlag Berlin Heidelberg.
Open Access
Phase retrieval from electric field intensity for wide angle optical fields
(OSA, 2017) Külçe, Onur; Onural, Levent
An intensity preserving scalar to vector electric field mapping, in a wave propagation environment, based on a filtering procedure is proposed. In a phase retrieval problem, the proposed mapping outperforms the conventional mapping.