Browsing by Subject "Graphene nanoplatelets"

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Open Access
Enhanced non-volatile memory characteristics with quattro-layer graphene nanoplatelets vs. 2.85-nm Si nanoparticles with asymmetric Al2O3/HfO2 tunnel oxide
(Springer New York LLC, 2015) El-Atab, N.; Turgut, B. B.; Okyay, Ali Kemal; Nayfeh, M.; Nayfeh, A.
In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al2O3/HfO2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al2O3/HfO2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics.
Open Access
Graphene Nanoplatelets Embedded in HfO2 for MOS Memory
(Electrochemical Society Inc., 2015) El-Atab, N.; Turgut, Berk Berkan; Okyay, Ali Kemal; Nayfeh, A.
In this work, a MOS memory with graphene nanoplatelets charge trapping layer and a double layer high-κ Al2O3/HfO2 tunnel oxide is demonstrated. Using C-Vgate measurements, the memory showed a large memory window at low program/erase voltages. The analysis of the C-V characteristics shows that electrons are being stored in the graphene-nanoplatelets during the program operation. In addition, the retention characteristic of the memory is studied by plotting the hysteresis measurement vs. time. The measured excellent retention characteristic (28.8% charge loss in 10 years) is due to the large electron affinity of the graphene. The analysis of the plot of the energy band diagram of the MOS structure further proves its good retention characteristic. Finally, the results show that such graphene nanoplatelets are promising in future low-power non-volatile memory devices.
Open Access
Novel materials for thin-film memory cells
(2014) Çimen, Furkan
The tremendous growth in consumer electronics market increased the need for low-cost, low-power and high quality memory chips. This challenge is further aggravated by the continuous increase in density and scaling of the gate length, since it creates a major challenge for current nonvolatile flash memory devices to maintain reliability and retention. Therefore, it is imperative to find new materials and novel fabrication processes to be incorporated in memory cells in order to keep up with the enormous rate of increase in consumer needs. In the first part of this thesis, we demonstrate a charge trapping memory with graphene nanoplatelets embedded in atomic layer deposited ZnO. We first introduce the fabrication process for the memory device and then investigate the memory characteristics. Our experimental analysis on the memory cell shows a large threshold voltage Vt shift (4V ) at low operating voltages (6/ − 6V ), good retention (> 10 years), and good endurance characteristics (> 104 cycles). The resulting memory behavior is also verified by theoretical computations. In the second part, we demonstrate the use of laser-synthesized indium-nitride nanoparticles (InN-NPs) as the charge trapping layer in the memory cell. We first introduce the indium-nitride nanoparticle synthesis and then detail the fabrication process of the memory device. The experimental analysis of the memory cell results in a noticeable threshold voltage Vt shift (2V ) at low operating voltages (4V ) in addition to the similar retention and endurance performance with the graphene-based memory cells. The memory behavior was also verified with theoretical computations for the InN-NPs based memory cells. In the last part of this thesis, we demonstrate a memory device with a gate stack fabricated in a single ALD step. Single-step all-ALD approach avoids the risk of contamination and incorporation of impurities in the gate stack. It also allows low-cost production by eliminating multiple equipment utilization. Motivated by these, we first present the fabrication process of the memory device and then explain the experimental and theoretical characterization and analysis. The memory effect of the thin-film ZnO charge-trapping memory cell is verified by a 2.35V hysteresis in drain current vs. gate voltage curve. The resulting memory behavior is also verified by physics-based TCAD simulations.