Browsing by Subject "Graph applications"
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Item Open Access Çizge uygulamalarına özel işlemci tasarımı(IEEE, 2022-08-29) Pulat, Gülce; Saeed, Aamir; Yenimol, Mehmetali Semi; Gülgeç, Utku; Öztürk, ÖzcanBir çok büyük veri işleme uygulaması “PageRank”, “İşbirliğine Dayalı Filtreleme” ve “Betweenness Centrality” gibi düzensiz ve yinelemeli çizge algoritmalarından yararlanmaktadır. Çizge yapılarında her bir düğüm bir kişiye ya da nesneye karşılık gelirken, her bir ayrıt da bir kişi ya da nesne çifti arasındaki ilişkiye karşılık gelmektedir. Böylesi büyük verileri işleyen algoritmaları yürütecek genel amaçlı işlemciler yetersiz kalabilmektedir. Özellikle, güç kısıtları sebebiyle işlemci alt parçalarından sadece bir kısmı aynı anda aktif olarak kullanılabilmektedir. Bu da işlemcinin etkin olarak kullanılmasına engel olarak aktif olmayan “karanlık silikon”lar ortaya çıkarmaktadır. Bu bildirinin amacı da büyük verili ve düzensiz çizge uygulamalarını hızlı, verimli ve kolay programlanabilir biçimde çalıştıracak bir işlemci mimarisi tasarlamaktır. Literatürde çizge uygulamaları için daha önce sunulmuş çalışmalar çoğunlukla sadece yazılım ya da hızlandırıcı seviyesindedir. İşlemci seviyesi tasarımlar ise donanımsal maliyet, talep ettikleri mimari destek ve komut seti değişiklikleri açılarından bu bildiri kapsamında tanıtılacak işlemciden farklıdır.Item Open Access Hardware/software Co-design of domain-specific RISC-V processor for graph applications(Bilkent University, 2022-05) Yenimol, Mehmetali SemiGraph applications are employed in many fields but show poor performance on general-purpose computing systems due to heavy, irregular, and data-driven memory access patterns. The diverse topology of real-life graphs also affects the performance. Even though many hardware accelerators have been proposed to mitigate performance issues and provide energy efficiency, programmability and flexibility have not been sufficiently addressed. This thesis presents a domain-specific processor design based on extending the RISC-V Instruction Set Architecture (ISA). The proposed approach uses new instructions supported by the compiler and software library. Micro-architectural design for executing the new instructions is based on a scratchpad-memory (SPM), prefetcher, and a non-blocking cache system. The custom processor is implemented using System Verilog HDL and simulated with Xilinx's Vivado Design Suite. LLVM Compiler Framework is used for compiler support and optimization. The software library for utilizing the custom instructions uses Gather-Apply-Scatter (GAS) paradigm. The system is evaluated on well-known graph benchmarks, while sensitivity analysis is done on various parameters for achieving the best performance with minimal cost. Performance is measured on both native benchmarks and the software library. In addition, compiler support is evaluated for its effect on performance. Cost-efficient performance evaluations show average speedups between 10% and 49% for different benchmarks, while the single-core architecture can achieve up to 73%.Item Open Access System-on-chip memory design for a domain-specific RISC-V processor(Bilkent University, 2023-05) Gülgeç, UtkuThe use of graph applications is common in many areas; however, irregular and data-driven memory access patterns combined with the large sizes of graph data results in performance loss in general-purpose computing systems. Existing studies proposed hardware accelerators often implemented on FPGAs to alleviate performance problems and improve energy efficiency while having less emphasis on programmability and flexibility. This thesis presents a hardware implementation of a domain-specific processor design for graph applications on a system-on-chip (SoC) platform accompanied by a design of a memory framework. The proposed system architecture improves the micro-architecture of a baseline design, integrates the baseline with an efficient system-on-chip bus communication protocol, and compares alternative memory framework implementations. The hardware is implemented on a state-of-the-art evaluation board. Popular graph benchmarks are used for performance evaluations of the implemented system, and various sensitivity analysis is done on newly added system parameters to determine the optimal system configuration. An analysis of power consumption and resource utilization is also provided. Overall, average speed-ups vary between 15% and 25% depending on the benchmark and graph data, while on-chip power consumption varies between 3.8 to 4.2 Watts depending on the system clock frequency.