Browsing by Subject "Field programmable gate arrays (FPGA)"

Now showing 1 - 7 of 7

Open Access
Autofocus method in thermal cameras based on image histogram
(IEEE, 2011) Turgay, E.; Teke, Oğuzhan
In this paper, a new histogram based auto-focusing method for thermal cameras is proposed. This proposed method is realized by FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) working together and simultaneously. HF (High Frequency) component, obtained from real-time image flow by FPGA and DSP is used for auto-focusing process. Proposed method is able to determine the focus direction from the HF component produced in the process of histogram equalization by FPGA, unlike Fourier transform and pixel differenve based methods in the literature. With this superiority, proposed method requires no extra calculation for thermal cameras for which histogram equalization is necessary. Analysis show that proposed method is successful on the simulations and scanning thermal cameras.
Open Access
Fiber laser-microscope system for femtosecond photodisruption of biological samples
(Optical Society of America, 2012-02-22) Yavaş, Seydi; Erdoğan, Mutlu; Gürel, Kutan; İlday, F. Ömer; Eldeniz, Y. B.; Tazebay, Uygar H.
We report on the development of a ultrafast fiber lasermicroscope system for femtosecond photodisruption of biological targets. A mode-locked Yb-fiber laser oscillator generates few-nJ pulses at 32.7 MHz repetition rate, amplified up to ~125 nJ at 1030 nm. Following dechirping in a grating compressor, ~240 fs-long pulses are delivered to the sample through a diffraction-limited microscope, which allows real-time imaging and control. The laser can generate arbitrary pulse patterns, formed by two acousto-optic modulators (AOM) controlled by a custom-developed fieldprogrammable gate array (FPGA) controller. This capability opens the route to fine optimization of the ablation processes and management of thermal effects. Sample position, exposure time and imaging are all computerized. The capability of the system to perform femtosecond photodisruption is demonstrated through experiments on tissue and individual cells.
Open Access
An FPGA implementation architecture for decoding of polar codes
(IEEE, 2011) Pamuk, Alptekin
Polar codes are a class of codes versatile enough to achieve the Shannon bound in a large array of source and channel coding problems. For that reason it is important to have efficient implementation architectures for polar codes in hardware. Motivated by this fact we propose a belief propagation (BP) decoder architecture for an increasingly popular hardware platform; Field Programmable Gate Array (FPGA). The proposed architecture supports any code rate and is quite flexible in terms of hardware complexity and throughput. The architecture can also be extended to support multiple block lengths without increasing the hardware complexity a lot. Moreover various schedulers can be adapted into the proposed architecture so that list decoding techniques can be used with a single block. Finally the proposed architecture is compared with a convolutional turbo code (CTC) decoder for WiMAX taken from a Xilinx Product Specification and seen that polar codes are superior to CTC codes both in hardware complexity and throughput. © 2011 IEEE.
Open Access
FPGA implementation of a fault-tolerant application-specific NoC design
(IEEE, 2016-04) Yeşil, Şerif; Tosun, S.; Öztürk, Özcan
Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem is fatal to application-specific Network-on-Chip (NoC) designs as well if they cannot tolerate such failures. One solution to this problem can be having alternative routing options on the network for each communicating pair. In this study, we present an FPGA implementation of such a method for application-specific NoCs. This method adds additional network resources to the non-fault-tolerant design in an attempt to make it fault-tolerant. We show the effects of the presented fault-tolerant method on an FPGA implementation of Mp3 encoder based on energy consumption and area increase against non-fault-tolerant case. © 2016 IEEE.
Open Access
JPEG hardware accelerator design for FPGA
(IEEE, 2007) Duman, Kaan; Çoǧun, Fuat; Öktem, L.
A fully pipelined JPEG hardware accelerator that runs on FPGA is presented. The accelerator is designed interactively in a simulation environment, using a DSP hardware design automation tool chain. The encoder part of the accelerator accepts 8×8 image blocks in a streaming fashion, and outputs the zigzag-scanned, quantized 2-D DCT coefficients of the block. The decoder part accepts zigzag-scanned, quantized DCT coefficients, and outputs reconstructed 8×8 image block. Each part has a throughput of one system clock per pixel per channel. The encoder employs a fast pipelined implementation for 2-D DCT [1]. For the decoder, a new pipelined 2-D IDCT structure is developed. Our IDCT structure is based on an IDCT factorization for software implementation [2], and is inspired by the pipelined DCT structure employed in the encoder. The resource utilization and maximum frequency figures for a particular FPGA target suggest that our accelerator has competitive performance.
Open Access
Proof-of-concept energy-efficient and real-time hemodynamic feature extraction from bioimpedance signals using a mixed-signal field programmable analog array
(IEEE, 2017) Töreyin, Hakan; Shah, S.; Hersek, S.; İnan, O. T.; Hasler, J.
We present a mixed-signal system for extracting hemodynamic parameters in real-time from noisy electrical bioimpedance (EBI) measurements in an energy-efficient manner. The proof-of-concept system consists of floating-gate-based analog signal processing (ASP) electronics implemented on a field programmable analog array (FPAA) chip interfaced with an on-chip low-power microcontroller. Physiological features important for calculating hemodynamic parameters (e.g., heart rate, blood volume, and blood flow) are extracted using the custom signal processing circuitry, which consumes a total power of 209 nW. Testing of the signal processing circuitry has been performed using ∼580 sec of an impedance plethysmography dataset collected from the knee of a subject using a custom analog EBI front-end. Results show the similarities of variations in heart rate, blood volume, and blood flow calculated using features extracted by the ASP circuitry implemented on an FPAA and a MATLAB digital signal processing algorithm.
Open Access
Reconfigurable hardened latch and flip-flop for FPGAs
(IEEE, 2017-07) Ahangari, Hamzeh; Alouani, I.; Öztürk, Özcan; Niar, S.
In this paper, we propose Joint Latch (JLatch) and Joint Flip-Flop (JFF), two novel reconfigurable structures which bring the reconfigurability of reliability to user latches and flip-flops (FFs) in reconfigurable devices such as FPGAs. Specifically, we implement two reconfigurable storage elements that exploit a trade-off between reliability and amount of available resources. In fault prone conditions, JLatch (or JFF) is configured in such a way that four pre-selected normal static latches (or FFs) are combined together at circuit level to form one hardened storage cell. Solution focuses on transient faults such as soft errors, where we show that critical charge is increased by at least three orders of magnitude (1000X) to practically bring immunity against any Single Event Upset (SEU). If four latches inside an FPGA logic block are far enough, it can effectively cope with Multiple Bit Upsets (MBUs) as well. Additionally, provided that special transistor sizing is applied (only necessary for some latch structures), JLatch and JFF take advantage of a novel self-correcting technique to correct any single fault immediately. Our solution provides reconfigurability of reliability with negligible performance and area overhead with only one (two) extra transistor(s) per latch (FF). The delay of this technique is less than the delay of conventional TMR (Triple Modular Redundancy) technique with a majority voter at output. © 2017 IEEE.