Browsing by Subject "Application specific network on chip"

Now showing 1 - 2 of 2

Open Access
Fault-tolerant topology generation method for application-specific network-on-chips
(Institute of Electrical and Electronics Engineers, 2015) Tosun, S.; Ajabshir, V. B.; Mercanoglu, O.; Ozturk, O.
As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks, which makes the entire chip useless. In this paper, we aim to make faulty chips designed with network-on-chip (NoC) communication usable. Specifically, we present fault-tolerant irregular topology-generation method for application-specific NoC designs. Designed NoC topology allows different routing path if there is a link failure on the default routing path. Additionally, we present a simulated annealing-based application mapping algorithm aiming to minimize total energy consumption of the NoC design. We compare fault-tolerant topologies with nonfault-tolerant application-specific irregular topologies on energy consumption, performance, and area using multimedia benchmarks and custom-generated graphs. Our results demonstrate that our method is able to determine fault-tolerant topologies with negligible area increase and better energy values.
Open Access
FPGA implementation of a fault-tolerant application-specific NoC design
(IEEE, 2016-04) Yeşil, Şerif; Tosun, S.; Öztürk, Özcan
Today's integrated circuits are more susceptible to permanent link failures than before as a result of diminishing technology sizes. Even a single link failure can make an entire chip useless. Single link failure problem is fatal to application-specific Network-on-Chip (NoC) designs as well if they cannot tolerate such failures. One solution to this problem can be having alternative routing options on the network for each communicating pair. In this study, we present an FPGA implementation of such a method for application-specific NoCs. This method adds additional network resources to the non-fault-tolerant design in an attempt to make it fault-tolerant. We show the effects of the presented fault-tolerant method on an FPGA implementation of Mp3 encoder based on energy consumption and area increase against non-fault-tolerant case. © 2016 IEEE.