Browsing by Subject "3-D integration"

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    Atomic Layer Deposition for Vertically Integrated ZnO Thin Film Transistors: Toward 3D High Packing Density Thin Film Electronics
    (Wiley-VCH Verlag, 2017) Sisman, Z.; Bolat, S.; Okyay, Ali Kemal
    We report on the first demonstration of the atomic layer deposition (ALD) based three dimensional (3D) integrated ZnO thin film transistors (TFTs) on rigid substrates. Devices exhibit high on-off ratio (∼106) and high effective mobility (∼11.8 cm2 V−1 s−1). It has also been demonstrated that the steps of fabrication result in readily stable electrical characteristics in TFTs, eliminating the need for post-production steps. These results mark the potential of our fabrication method for the semiconducting metal oxide-based vertical-integrated circuits requiring high packing density and high functionality. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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    OptMem: dark-silicon aware low latency hybrid memory design
    (IEEE, 2016-01) Onsori, Salman; Asad, Arghavan A; Raahemifar, K.; Fathy, M.
    In this article, we present a convex optimization model to design a three dimension (3D)stacked hybrid memory system to improve performance in the dark silicon era. Our convex model optimizes numbers and placement of static random access memory (SRAM) and spin-Transfer torque magnetic random-Access memory(STT-RAM) memories on the memory layer to exploit advantages of both technologies. Power consumption that is the main challenge in the dark silicon era is represented as a main constraint in this work and it is satisfied by the detailed optimization model in order to design a dark silicon aware 3D Chip-Multiprocessor (CMP). Experimental results show that the proposed architecture improves the energy consumption and performanceof the 3D CMPabout 25.8% and 12.9% on averagecompared to the Baseline memory design. © 2016 IEEE.