Browsing by Author "Pamuk, Alptekin"

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Open Access
An FPGA implementation architecture for decoding of polar codes
(IEEE, 2011) Pamuk, Alptekin
Polar codes are a class of codes versatile enough to achieve the Shannon bound in a large array of source and channel coding problems. For that reason it is important to have efficient implementation architectures for polar codes in hardware. Motivated by this fact we propose a belief propagation (BP) decoder architecture for an increasingly popular hardware platform; Field Programmable Gate Array (FPGA). The proposed architecture supports any code rate and is quite flexible in terms of hardware complexity and throughput. The architecture can also be extended to support multiple block lengths without increasing the hardware complexity a lot. Moreover various schedulers can be adapted into the proposed architecture so that list decoding techniques can be used with a single block. Finally the proposed architecture is compared with a convolutional turbo code (CTC) decoder for WiMAX taken from a Xilinx Product Specification and seen that polar codes are superior to CTC codes both in hardware complexity and throughput. © 2011 IEEE.
Open Access
Low complexity equalization for OFDM in doubly selective channels
(2009) Pamuk, Alptekin
In current standards Orthogonal Frequency Division Multiplex -OFDM- is widely used for its high resistance to multi-path environments and high spectral ef- ficiency. However since the transmission duration is longer, it is affected from time variations of the channel more than single carrier systems. Orthogonality of sub-carriers are lost within an OFDM symbol and intercarrier interference(ICI) occurs as a result of time variation of the channel. Channel estimation and equalization become problematic, because the classical structures like MMSE require very complex operations. This thesis studies the channel equalization problem, as separate from the channel estimation problem. The thesis assumes that the channel coefficients are perfectly known and focuses on the estimation of data transmitted on each OFDM carrier. First, a survey of existing algorithms on channel equalization is given and simulations are provided to compare them in terms of complexity and performance under an OFDM system scenario that is consistent with the present WiMAX system parameters and operating conditions. As a novel contribution, the thesis proposes two new equalization methods by amending existing algorithms and shows that these modified algorithms improve the state-of-the-art in channel equalization in terms of complexity andperformance under certain high-mobility scenarios. Finally it is shown that the intercarrier interference cancellation problem remains a major impediment to the implementation of OFDM in high-mobility environments.
Open Access
A two phase successive cancellation decoder architecture for polar codes
(IEEE, 2013) Pamuk, Alptekin; Arıkan, Erdal
We propose a two-phase successive cancellation (TPSC) decoder architecture for polar codes that exploits the array-code property of polar codes by breaking the decoding of a length-TV polar code into a series of length-√ L decoding cycles. Each decoding cycle consists of two phases: a first phase for decoding along the columns and a second phase for decoding along the rows of the code array. The reduced decoder size makes it more affordable to implement the core decoder logic using distributed memory elements consisting of flip-flops (FFs), as opposed to slower random access memory (RAM), leading to a speed up in clock frequency. To minimize the circuit complexity, a single decoder unit is used in both phases with minor modifications. The re-use of the same decoder module makes it necessary to recall certain internal decoder state variables between decoding cycles. Instead of storing the decoder state variables in RAM, the decoder discards them and calculates them again when needed. Overall, the decoder has O(√ L) circuit complexity excluding RAM, and a latency of approximately 2.57V. A RAM of size O(N) is needed for storing the channel log-likelihood variables and the decoder decision variables. As an example of the proposed method, a length N = 214 bit polar code is implemented in an FPGA and the synthesis results are compared with a previously reported FPGA implementation. The results show that the proposed architecture has lower complexity, lower memory utilization with higher throughput, and a clock frequency that is less sensitive to code length. © 2013 IEEE.