Browsing by Author "Çankaya Akoğlu, Büşra"

Now showing 1 - 3 of 3

Open Access
60W stacked-HEMT based asymmetric X-band GaN SPDT switch for single chip T/R modules
(IEEE - Institute of Electrical and Electronics Engineers, 2023-10-25) Ertürk, Volkan; Gürdal, Armağan; Çankaya Akoğlu, Büşra; Özbay, Ekmel
This paper presents a high-power, asymmetric single-pole double-throw (SPDT) monolithic microwave integrated circuit (MMIC) switch using high electron mobility transistors (HEMT) with AlGaN/GaN technology for single chip X-band T/R modules. The SPDT switch is designed in series-shunt topology for high-power handling and low-loss performance. For high-power handling, shunt-stacked HEMTs on the transmit (Tx) path and series-stacked HEMTs on the receive (Rx) path are used. In its Tx mode, the switch has achieved an insertion loss better than 0.75 dB throughout the 6-13 GHz bandwidth with a return loss of 14 dB and an isolation of 28 dB. It can handle more than 60 W RF input power at 0.1 dB compression. In its Rx mode, the switch can receive signals with an insertion loss lower than 1.15 dB with 14 dB return loss and 19 dB isolation. With its low insertion and high-power handling capacity from C-band to Ku-band, this switch shows state-of-the-art performance for communication systems.
Open Access
AlGaN/GaN-Based laterally gated high-electron-mobility transistors with optimized linearity
(IEEE, 2021-02-01) Odabaşı, Oğuz; Yılmaz, Doğan; Aras, Erdem; Asan, Kübra Elif; Zafar, Salahuddin; Çankaya Akoğlu, Büşra; Bütün, Bayram; Özbay, Ekmel
In this work, highly linear AlGaN/GaN laterally gated (or buried gate) high-electron-mobility transistors (HEMTs) are reported. The effect of gate dimensions on source-access resistance and the linearity of laterally gated devices are investigated experimentally in detail for the first time. Transistors with different gate dimensions and conventional planar devices are fabricated using two-step electron beam lithography (EBL). Current-voltage, source-access resistance, small-signal, and two-tone measurements are performed to evaluate the linearity of devices. Contrary to conventional planar HEMTs, the intrinsic transconductance of laterally gated devices monotonically increases with increasing gate voltage, showing a similar behavior as junction field-effect transistors (FETs). The source-access resistance shows a polynomial increase with the drain current, which can be reduced by decreasing the filling ratio of the buried gates. Through the optimization of these two competing factors, i.e., intrinsic transconductance and the source-access resistance, flat transconductance with high linearity is achieved experimentally. The laterally gated structure shows flat transconductance and small-signal power gain over a larger span of gate voltage that is 2.5 times higher than a planar device. Moreover, 6.9-dB improvement in output intercept point (OIP3)/P DC is achieved. This approach can be used to improve the linearity of AlGaN/GaN HEMTs at the device level.
Open Access
Design and robustness improvement of high-performance LNA using 0.15 μm GaN technology for X-band applications
(John Wiley & Sons Ltd., 2022-07) Zafar, Salahuddin; Çankaya Akoğlu, Büşra; Aras, Erdem; Yılmaz, Doğan; Nawaz, Muhammad İmran; Kashif, Ahsanullah; Özbay, Ekmel
In this paper, we present a highly robust GaN-based X-band low-noise amplifier (LNA) showing promising small-signal and noise performance as well as good linearity. The LNA is fabricated using in-house 0.15 μm AlGaN/GaN on a SiC HEMT process. Owing to the optimum choice of HEMT topologies and simultaneous matching technique, LNA achieves a noise figure better than 2 dB, output power at 1 dB gain compression higher than 19 dB, input and output reflection coefficients better than −9 and −11 dB, respectively. The small-signal gain of LNA is more than 19 dB for the whole band, and NF has a minimum of 1.74 dB at 10.2 GHz. LNA obtains an OIP3 up to 34.2 dBm and survives input power as high as 42 dBm. Survivability is investigated in terms of gain compression and forward gate current. Reverse recovery time (RRT), a crucial parameter for radar front-ends, is explored with respect to the RC time constant and trap phenomenon. The analysis shows that the significant contribution in RRT is due to traps while the RC time constant is in the nanoseconds range. Moreover, this study also addresses the requirement and choice of a DC gate feed resistor for the subsequent stages in a multi-stage design. The size of the designed LNA chip is 3 mm (Formula presented.) 1.2 mm only.